Special Tracking Pool for Core L1 Cache Invalidate Latency
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Solution Overview
Problem
In computing environments with multiple processors sharing caches, cross-core invalidation mechanisms introduce latency in cache accesses due to the need for explicit responses, which can hinder performance, especially when the local cache is processing numerous invalidate requests.
Innovation Solution
Implementing a special tracking pool enhancement for core local cache (L1) address invalidates, where a separate allocation in the queue is reserved for read-only invalidate requests, allowing performance-sensitive hardware controllers to proceed without waiting for a response from the local cache, thereby reducing latency and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cross-core invalidation mechanisms are used to ensure cache coherency, then data consistency is improved, but cache access latency increases
Solution Approach 1:
The invalidate queue is segmented into two separate allocations: a first allocation for general invalidate requests that require responses, and a second allocation (special pool) for read-only invalidate requests that do not require responses. This segmentation allows performance-sensitive controllers to use the second allocation and proceed without waiting for responses, thereby reducing latency while maintaining data consistency through the first allocation.
2Reliability
If the local cache processes numerous invalidate requests, then cache coherency is maintained, but processing throughput decreases
Solution Approach 1:
The invalidate queue is divided into two separate allocations: a first allocation for general invalidate requests and a second allocation (special pool) exclusively for read-only invalidate requests. This segmentation allows the cache to process read-only invalidates asynchronously without blocking other operations, thereby maintaining cache coherency while improving overall processing throughput.
Solution Approach 2:
By allowing performance-sensitive hardware controllers to submit read-only invalidate requests to the second allocation and immediately proceed with subsequent operations, the system maintains continuous useful action without interruption. The invalidate requests are processed in the background, ensuring cache coherency is maintained while preventing stalls in the processing pipeline.
3Reliability
If hardware controllers wait for invalidate request responses, then data accuracy is ensured, but controller availability decreases
Solution Approach 1:
The invalidate queue is segmented into two allocations: the first allocation handles invalidate requests that require responses to ensure data accuracy, while the second allocation (special pool) handles read-only invalidate requests that do not require responses. This segmentation allows controllers using the second allocation to immediately become available for subsequent operations while data accuracy is maintained through the response-required first allocation.
Data Source
AI summary
Embodiments are for special tracking pool enhancement for core L1 address invalidates. An invalidate request is designated to fill an entry in a queue in a local cache of a processor core, the queue including a first allocation associated with processing any type of invalidate request and a second allocation associated with processing an invalidate request not requiring a response in order for a controller to be made available, the entry being in the second allocation. Responsive to designating the invalidate request to fill the entry in the queue in the local cache, a state of the controller that made the invalidate request is changed to available based at least in part on the entry being in the second allocation.