Spectral Shaping of Reference Clock Signals for Jitter Reduction
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Solution Overview
Problem
Sigma-delta analogue-digital converters are sensitive to clock signal jitters, which introduce noise into the feedback signal due to fluctuations in the reference clock signal, particularly affecting current-controlled digital-analogue converters.
Innovation Solution
A spectrally shaping apparatus and method that detects clock signal jitter and modulates the pulse widths of the reference clock signal using a detection circuit and modulation circuit, incorporating a switched-capacitor and current-controlled digital-analogue converter to integrate and quantify jitter, allowing for noise reduction by shifting conversion errors to non-data frequency ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current-controlled digital-analogue converters are used, then conversion speed is improved, but sensitivity to clock signal jitter increases
Solution Approach 1:
The patent detects clock signal jitter and uses it to modulate the pulse widths of clock pulses, converting the harmful jitter effect into a beneficial spectral shaping mechanism. The detected jitter information is fed back to adjust pulse widths, transforming the noise source into a controlled modulation signal that shifts errors to non-data frequency ranges.
Solution Approach 2:
The patent changes the pulse width parameter of clock pulses based on detected jitter characteristics. By dynamically adjusting the pulse width parameter in response to jitter detection, the system compensates for the harmful effects of clock signal variations while maintaining the fast conversion speed of current-controlled DACs.
2Device complexity
If reference clock signal precision is reduced, then device complexity is decreased, but noise and distortion increase
Solution Approach 1:
The patent implements a feedback mechanism where clock signal jitter is detected and used to modulate subsequent clock pulses. This feedback loop allows the use of less precise reference clock generators while maintaining signal quality, as the jitter is continuously measured and compensated through pulse width modulation.
Solution Approach 2:
The patent introduces an intermediary detection circuit that measures clock signal jitter and translates it into modulation signals. This intermediary component bridges the gap between imperfect clock sources and the converter, allowing noise and distortion to be managed without requiring high-precision clock generators.
3Object-affected harmful factors
If switched-capacitor digital-analogue converters are used, then immunity to clock signal jitter is improved, but conversion speed decreases
Solution Approach 1:
The patent merges the advantages of both switched-capacitor and current-controlled approaches. It uses current-controlled DACs for fast conversion while incorporating jitter detection and spectral shaping techniques that provide the jitter immunity characteristic of switched-capacitor designs, achieving a hybrid solution that combines speed and robustness.
Data Source
AI summary
Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).