Spectral Test Point Insertion for IC Testability
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Solution Overview
Problem
Current methods for testing integrated circuits, such as full-scan and partial-scan designs, are inefficient in reducing the cost of testing and improving testability, as they require extensive manual intervention and result in high test data volumes and application times.
Innovation Solution
The use of gradient descent and linear programming algorithms to insert test points and scanned flip-flops into digital circuits, combined with spectral and entropy analysis, to optimize the placement of design-for-testability hardware, thereby reducing the amount of additional circuit hardware needed and enhancing testability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full-scan or partial-scan designs are used to improve testability, then test coverage is improved, but test data volume and application time increase significantly
Solution Approach 1:
The patent transforms the test application process by changing the parameter of test data representation through Fourier transform and spectral analysis. By converting time-domain test patterns into frequency-domain spectral signatures, the system achieves compact representation that reduces test data volume while maintaining complete test coverage through the information-preserving properties of spectral transformation.
Solution Approach 2:
The patent creates a spectral copy of the test patterns instead of directly applying time-domain patterns. By generating and applying spectral signatures that contain equivalent test information, the system reduces the amount of data that must be stored and transmitted while achieving the same fault detection capability through inverse spectral transformation during test application.
2Reliability
If extensive test hardware is added to every flip-flop to improve testability, then test coverage is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the test functionality from the time-domain pattern generation and application hardware, separating it into a spectral domain processing system. By moving the test information representation to the frequency domain, the system eliminates the need for complex time-domain pattern storage and application circuits, retaining only essential spectral transformation components.
Solution Approach 2:
The spectral analysis and transformation apparatus serves multiple functions: it compactly represents test patterns, enables efficient storage, facilitates rapid application through inverse transformation, and provides fault signature analysis capability. This multi-functional approach replaces multiple separate hardware subsystems with a unified spectral processing framework.
3Reliability
If manual intervention is used for test point and scan flip-flop insertion to optimize testability, then test coverage is improved, but productivity and automation level decrease
Solution Approach 1:
The patent implements an automated system that performs spectral analysis of the circuit design, automatically identifies optimal test points and scan flip-flop locations, and generates the necessary test infrastructure code without human intervention. The spectral-based metrics and algorithms autonomously determine the minimal hardware configuration required to achieve complete test coverage, eliminating manual analysis and design steps.
Solution Approach 2:
The patent replaces manual mechanical processes of test point selection and scan chain design with automated spectral analysis algorithms. By using Fourier transform-based metrics and computer-aided design tools, the system automatically computes testability parameters, identifies critical paths, and generates optimized test configurations, substituting human expert analysis with systematic computational methods.
4Reliability
If conventional ATPG methods are used to generate test patterns, then fault coverage is achieved, but computation time is excessive
Solution Approach 1:
The patent applies periodic spectral analysis techniques that transform the continuous, computationally intensive ATPG process into discrete frequency-domain operations. By using Fourier-based methods to analyze circuit behavior at different frequency components, the system efficiently identifies test requirements without exhaustive time-domain simulation, reducing computation time while maintaining comprehensive fault coverage.
Data Source
AI summary
Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT). The methods limit the amount of additional circuit hardware for test points and scan flip-flops.