Speculative Address Translation Requests to Reduce PCIe Traffic
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Solution Overview
Problem
Existing SSDs in multi-tenancy systems experience increased PCIe bus traffic due to the complexity and performance degradation caused by Address Translation Service (ATS) requests, which are not speculative and involve physical region page (PRP) or scatter gather list (SGL) host pointer fetching.
Innovation Solution
Implementing speculative address translation requests based on the history and structure of host buffer pointers, coalescing these with normal requests by dynamically changing the length field, and collecting statistics to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If speculative address translation requests are issued based on history and structure of host buffer pointers, then data retrieval performance is improved, but device complexity increases
Solution Approach 1:
The controller issues speculative address translation requests in advance based on the history and structure of host buffer pointers before the actual data transfer occurs. This preliminary action allows the translation to be completed beforehand, improving data retrieval performance when the actual transfer happens.
Solution Approach 2:
The controller dynamically adjusts the length field in address translation request packets to coalesce multiple speculative requests. This dynamic modification optimizes the aggregation of requests while managing the increased complexity through adaptive control mechanisms.
2Quantity of substance
If speculative address translation requests are coalesced with normal requests by dynamically changing the length field, then PCIe bus traffic is reduced, but manufacturing precision of protocol compliance decreases
Solution Approach 1:
The controller merges multiple speculative address translation requests with normal requests into a single PCIe transaction by dynamically adjusting the length field. This coalescing reduces the number of separate transactions on the PCIe bus, thereby reducing overall bus traffic while maintaining protocol compliance through controlled modification.
3Productivity
If the controller collects statistics of speculative address translation requests per tenant, then performance optimization is improved, but device complexity increases
Solution Approach 1:
The controller collects statistics on speculative address translation requests per tenant and uses this feedback information to optimize future speculative requests. This feedback mechanism enables the controller to learn from past behavior patterns and improve performance over time while managing complexity through structured data collection.
Data Source
AI summary
Reducing extra traffic on the PCIe bus by initiating speculative address translation requests and aggregating them with normal address translation request can lead to significantly improved data retrieval performance. This can be achieved by issuing speculative address translation requests based on history or structure of host buffer pointers previously issued by each tenant. If the device controller determines that there is a high-hit rate probability, the controller will coalesce the speculative requests with the normal address translation request. The coalescing may be accomplished by dynamically changing the length field in the address translation request. The controller may also collect statistics of the speculative address translation requests per tenant. If the controller determines that the performance gain for a specific tenant's workload becomes minimal, the speculative request feature is disabled.