Speculative CMOS DFE Circuit for Low-Latency Feedback
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Solution Overview
Problem
High-speed data communication systems face challenges in reducing latency in Decision Feedback Equalizers (DFE) implemented with CMOS logic, as existing techniques struggle to meet the low latency requirements necessary for high data rates, particularly when transitioning from current-mode logic (CML) to CMOS circuits, which often result in increased power and area consumption.
Innovation Solution
A CMOS implementation of a speculative digital feedback loop that merges a multiplexer and latch into a single circuit, using a passgate multiplexer and regenerative buffer to maintain output during precharge periods, reducing the critical path timing requirements and allowing replacement of CML stages with CMOS stages, thereby achieving lower latency and power/area benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If CML stages are replaced with CMOS stages to reduce power and area consumption, then power and area are reduced, but latency increases
Solution Approach 1:
The patent merges the multiplexer and latch into a single integrated circuit stage, eliminating the need for separate CML stages. This consolidation allows the use of CMOS logic throughout the feedback loop while maintaining timing requirements, as the combined circuit performs both selection and storage functions in one low-latency stage that meets the 1 UI latency budget.
Solution Approach 2:
The integrated circuit performs multiple functions simultaneously - it acts as both a multiplexer (selecting between speculative paths) and a latch (storing the selected value). This multi-functionality eliminates the need for dedicated CML stages that would otherwise be required for high-speed operation, enabling universal CMOS implementation across all DFE stages.
2Loss of time
If the number of stages within the feedback loop is minimized to reduce latency, then latency is reduced, but circuit functionality becomes more complex
Solution Approach 1:
The patent combines the multiplexer and latch into a single integrated circuit stage, reducing the total number of stages in the feedback loop. This merger minimizes the critical path delay while consolidating multiple functions into one unit, thereby reducing overall circuit complexity rather than increasing it.
Solution Approach 2:
The integrated circuit performs multiple functions simultaneously - it acts as both a multiplexer (selecting between speculative paths) and a latch (storing the selected value). This multi-functionality eliminates the need for dedicated CML stages that would otherwise be required for high-speed operation, enabling universal CMOS implementation across all DFE stages.
3Loss of time
If speculative DFE technique is used to replace analog loop with digital loop, then latency requirements are relaxed, but analog settling time requirements are eliminated only for static taps
Solution Approach 1:
The patent merges the multiplexer and latch into a single integrated circuit stage, eliminating the need for separate CML stages. This consolidation allows the use of CMOS logic throughout the feedback loop while maintaining timing requirements, as the combined circuit performs both selection and storage functions in one low-latency stage that meets the 1 UI latency budget.
Data Source
AI summary
A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.