Speculative Data Return Concurrent to Invalidate Request

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Solution Overview

Problem

In computing environments with multiple processors sharing caches, cross-core intervention for cache coherency leads to increased latency, as processors must wait for invalidation responses before accessing shared cache lines, impacting performance.

Innovation Solution

Concurrently sending a speculative data request and an invalidate request to the owning processor, allowing the requesting processor to use the data before receiving a response, and later validating or rolling back operations based on the invalidate response.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cross-core intervention is used to ensure cache coherency, then data integrity is maintained, but cache access latency increases

Engineering Contradiction:

Improvedata coherencyVSAvoidcache access latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by sending the invalidate request concurrently with the data request rather than sequentially. The shared cache controller initiates the invalidate request to the owning processor at the same time it retrieves the data, so that by the time the data is needed, the invalidation has already been processed. This eliminates the waiting period and reduces cache access latency while maintaining data coherency.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If sequential processing of data request and invalidate request is used, then data coherency is ensured, but system performance decreases

Engineering Contradiction:

Improvedata coherencyVSAvoidsystem performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent merges the data request and invalidate request into a single concurrent operation. Instead of processing them as separate sequential steps, the shared cache controller combines both requests and sends them simultaneously to the appropriate processors. This merging of operations reduces the total processing time and improves system performance while ensuring data coherency through the speculative validation mechanism.

Inventive Principle:

Principle #5Merging (Combining)

3Loss of time

If speculative data access is allowed, then cache latency is reduced, but data validity verification complexity increases

Engineering Contradiction:

Improvecache latencyVSAvoidvalidation complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements feedback by having the shared cache controller monitor whether the owning processor has completed its invalidate operation before allowing the requesting processor to use the speculative data. The controller receives feedback from the owning processor about the invalidation status and uses this information to validate or invalidate the speculative data. This feedback mechanism simplifies the validation process compared to complex hardware circuits while maintaining data correctness.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10795824B2Speculative data return concurrent to an exclusive invalidate request

Publication Date: 2020.10.06 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Speculative data return in parallel with an exclusive invalidate request. A requesting processor requests data from a shared cache. The data is owned by another processor. Based on the request, an invalidate request is sent to the other processor requesting the other processor to release ownership of the data. Concurrent to the invalidate request being sent to the other processor, the data is speculatively provided to the requesting processor.