Speculative Egress Data Forwarding in Packet Switches
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Solution Overview
Problem
Current packet switching technologies face challenges in reducing latency within data networks, as header processing and queuing induce significant delays, and existing low-latency paths often come at the cost of increased circuitry and area requirements.
Innovation Solution
The implementation of speculative egress data forwarding in packet switches, which allows for preemptive transfer of packets via a low-latency 'Turbo Path' while maintaining a fallback option through a descriptor queue, enabling efficient data transfer by bypassing the descriptor queue and validating sequence numbers for successful transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If packets are transferred through the traditional descriptor queue path, then reliability is ensured, but latency increases
Solution Approach 1:
The patent implements preliminary action by preemptively transferring packet segments through the turbo path before the descriptor queue processing is complete. The system speculatively forwards segments based on sequence numbers and validation criteria, and only if validation fails does it fall back to the traditional descriptor queue path, thus achieving low latency while maintaining reliability.
Solution Approach 2:
The patent changes the routing parameter dynamically based on validation results. When sequence number validation succeeds, the packet is routed through the low-latency turbo path; when validation fails, it falls back to the reliable descriptor queue path. This parameter-based routing decision resolves the contradiction between speed and reliability.
2Speed
If a low-latency Turbo Path is implemented, then packet transfer speed increases, but switch area increases
Solution Approach 1:
The patent segments packets into multiple segments that can be independently transferred through the turbo path. By segmenting packets and transferring them in parallel without waiting for complete descriptor processing, the system achieves high-speed transfer without requiring a completely separate dedicated path for each packet, thus limiting the increase in switch area.
Solution Approach 2:
The turbo path shares the same crossbar switching fabric and physical infrastructure with the traditional path, making the switching core multi-functional. The same hardware resources serve both the low-latency turbo path and the reliable descriptor queue path, avoiding the need for duplicate dedicated circuitry and thus minimizing the increase in switch area.
3Loss of time
If packets are transferred without reading descriptors, then latency is reduced, but validation complexity increases
Solution Approach 1:
The patent performs preliminary validation of sequence numbers before transferring segments through the turbo path. By checking sequence numbers in advance and maintaining validation state, the system can quickly verify packet integrity without reading complete descriptors, reducing processing time while managing validation complexity through incremental checking.
Solution Approach 2:
The patent introduces sequence numbers as an intermediary validation mechanism. Instead of reading and validating complete packet descriptors (which would increase latency), the system uses compact sequence number fields as intermediaries to verify packet ordering and integrity. This intermediary approach simplifies the validation process while maintaining correctness.
Data Source
AI summary
A switching device includes ingress ports, egress ports, and switching circuits that connect the ingress ports with the egress ports. The switching device segments data included in a packet received at an ingress port into a plurality of segments. The switching device transfers the plurality of segments to an egress port via a data path included in the switching circuits, according to a first mode of routing the packet in an absence of reading a descriptor corresponding to the packet. The switching device orders, using port logic associated with the egress port, the segments and provides sequence numbers associated with the ordered segments to port logic associated with the ingress port. The switching device validates the transfer of the plurality of segments according to the first mode based on verifying that the sequence numbers satisfy at least one criterion.