Speculative Execution Predictor for Memory Access Correlation

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Solution Overview

Problem

In processor design, speculative execution leads to inefficiencies due to incorrect data loading from memory access instructions, as address correlations are not detected until execution, causing re-execution and pipeline refresh, which increases idle cycles and reduces performance.

Innovation Solution

A processor core with a speculative execution predictor that marks memory access instructions based on address correlations, adjusting their send order to prevent incorrect execution and eliminating the need for re-execution and pipeline refresh.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If speculative execution is implemented to improve processor performance, then instruction throughput is improved, but address correlation detection failure causes incorrect data loading and re-execution

Engineering Contradiction:

Improveinstruction throughputVSAvoiddata loading accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent performs address correlation detection during the instruction fetch stage, before the memory access instructions are executed. The speculative execution predictor compares program counters of memory access instructions with table entries to identify address correlations in advance, marking instructions that may have correlation issues before they reach the execution unit. This preliminary detection prevents incorrect speculative execution while maintaining high instruction throughput.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If address correlation detection is performed during execution, then data accuracy is maintained, but idle cycles increase and performance decreases

Engineering Contradiction:

Improvedata accuracyVSAvoidprocessor performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent moves address correlation detection from the execution stage to the instruction fetch stage. By comparing program counters and marking instructions with potential address correlations before execution, the system avoids idle cycles during execution while maintaining data accuracy. The scheduler unit then uses these marks to adjust instruction send order, preventing incorrect execution without stalling the pipeline.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If pipeline refresh is performed to clear incorrectly speculated instructions, then speculation errors are corrected, but performance loss increases

Engineering Contradiction:

Improvespeculation error correctionVSAvoidperformance loss

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs address correlation detection and instruction marking during the fetch stage, before incorrect speculative execution occurs. By identifying and marking instructions with address correlations in advance, the system prevents speculation errors rather than correcting them after they happen. This eliminates the need for pipeline refresh operations, avoiding the associated performance loss while maintaining reliability.

Inventive Principle:

Principle #10Preliminary action

4Productivity

If deeper pipeline is used to increase instruction throughput, then productivity is improved, but performance loss from speculation failure increases

Engineering Contradiction:

Improveinstruction throughputVSAvoidperformance loss from speculation failure

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent implements address correlation detection in the instruction fetch stage, allowing deeper pipelines to maintain high throughput while preventing speculation errors before they occur. By marking instructions with potential address correlations early in the pipeline, the system enables deeper pipelines without proportionally increasing performance loss from speculation failures, as the marking mechanism prevents incorrect execution regardless of pipeline depth.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11429391B2Speculative execution of correlated memory access instruction methods, apparatuses and systems

Publication Date: 2022.08.30 ALIBABA GROUP HOLDING LTD

AI summary

A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent. In the execution unit, the memory access instructions are executed according to the send order. This helps avoiding re-execution of a memory access instruction due to an address correlation of the memory access instruction. Consequently, this eliminates the need of adding an idle cycle in an instruction pipeline and the need of refreshing the pipeline to clear a memory access instruction that is incorrectly speculated.