Speculatively Inaccessible Cacheable Memory Type
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Solution Overview
Problem
Modern CPUs face security risks due to speculative execution, which allows malicious code to access impermissible memory locations and exploit side channels, making it difficult to protect sensitive data from attacks like Meltdown and Spectre.
Innovation Solution
A new memory type is introduced that is both cacheable and inaccessible by speculative instructions, ensuring that sensitive data is only accessed by privileged processes and not exposed through speculative execution, thereby preventing side-channel attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If speculative execution is enabled to improve instruction throughput, then processing speed is improved, but security vulnerabilities arise allowing access to impermissible memory locations
Solution Approach 1:
The patent segments memory into distinct types with different access permissions. Specifically, it introduces a new memory type (e.g., memory type 0x70 or higher) that is separated from conventional cacheable memory, allowing the system to maintain speculative execution for general purposes while restricting speculative access to sensitive memory regions through explicit permission bits in page table entries.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a memory management unit (MMU) that mediates between speculative execution requests and actual memory access. The MMU checks permission bits in page table entries to determine whether speculative loads are permitted, blocking such accesses to sensitive memory locations while allowing them for safe regions, thus resolving the security-throughput contradiction.
2Productivity
If speculative loads are performed to improve execution efficiency, then processing efficiency is improved, but side-channel attacks become possible through cache timing analysis
Solution Approach 1:
The patent applies local quality by assigning different security characteristics to different memory regions. Conventional cacheable memory (types 0x00-0x6F) allows speculative loads with full caching benefits, while sensitive memory regions (types 0x70 and higher) have speculative loads blocked at the MMU level. This localized differentiation maintains execution efficiency for non-sensitive operations while preventing side-channel attacks on sensitive data.
Solution Approach 2:
The patent changes the permission parameter in page table entries to control speculative access behavior. By setting specific permission bits (e.g., PCID=1 combined with other permission bits) for sensitive memory regions, the system dynamically controls whether speculative loads are permitted, thereby adjusting the balance between execution efficiency and security based on memory region characteristics.
3Speed
If memory is made cacheable to improve access speed, then memory access speed is improved, but speculative execution can exploit cache presence to leak information
Solution Approach 1:
The patent segments cacheable memory into secure and non-secure regions based on memory type and permission bits. Sensitive memory regions (types 0x70 and higher) have their speculative loads blocked at the MMU level before cache access occurs, preventing information leakage through cache timing while maintaining fast cacheable access for non-sensitive regions. This segmentation allows the system to preserve caching benefits where safe while blocking speculative exploitation where sensitive.
Data Source
AI summary
An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.