Speculative Interrupt Signalling for Latency Reduction
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Solution Overview
Problem
In real-time processing systems, existing interrupt controllers face significant latency in identifying the highest priority interrupt (HPPI) due to the comparison of multiple priority levels, which delays interrupt processing and can lead to pathological conditions from repeated incorrect speculative triggering.
Innovation Solution
The system employs an interrupt signal receiver and a priority level arbitrator that operate in parallel with trigger circuitry to initiate interrupt processing before the arbitration-completed time, speculating on the HPPI and allowing early trigger signal assertion, with a mask circuitry to filter out lower-priority interrupts and ensure reversible state changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If priority arbitration is performed sequentially before interrupt processing, then accurate HPPI identification is achieved, but interrupt latency increases
Solution Approach 1:
The trigger circuitry performs preliminary action by asserting the trigger signal before the priority level arbitrator completes its determination of the highest priority interrupt. This allows interrupt processing to be initiated in advance, reducing interrupt latency while maintaining accurate HPPI identification through subsequent verification
2Loss of time
If interrupt processing is initiated early before arbitration completion, then interrupt latency is reduced, but incorrect speculation may occur
Solution Approach 1:
The system implements feedback by having the priority level arbitrator complete its determination after the trigger signal is asserted. The result of the arbitration is fed back to verify whether the speculatively triggered interrupt was indeed the highest priority interrupt, allowing the system to correct incorrect speculation
Solution Approach 2:
The trigger circuitry performs preliminary action by asserting the trigger signal before the priority level arbitrator completes its determination. This preliminary interruption initiation reduces latency while the subsequent arbitration result verification ensures reliability
Data Source
AI summary
A data processing system includes an interrupt controller having a priority level arbitrator and trigger circuitry. The priority level arbitrator and the trigger circuitry operate in parallel to process interrupt signals received by an interrupt signal receiver. The trigger circuitry generates a trigger signal initiating interrupt processing before the priority level arbitrator has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.