Speculative Load Queue Cache Coherency Protocol for Side Channel Attack Mitigation

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Solution Overview

Problem

Speculative execution in processors leads to permanent changes in microarchitectural structures, which can be exploited for side channel attacks, leaking confidential information and violating security assumptions in software security mechanisms.

Innovation Solution

Implementing a cache coherency protocol that prevents changes to microarchitectural states during speculative execution by using a speculative-modified state to track speculative loads and ensure that cache state changes only occur after the correctness of speculative execution is confirmed, thereby preventing side channel attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If speculative execution is implemented to enhance processing efficiency, then productivity is improved, but security is worsened due to side channel attacks leaking confidential information

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidside channel attacks

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the cache state into two distinct states: speculative-modified state for addresses accessed during speculative execution and modified state for confirmed addresses. This segmentation allows the system to track and differentiate between speculative and non-speculative cache accesses, preventing side channel attacks while maintaining speculative execution performance benefits

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a speculative-modified state as an intermediary state between invalid and modified states in the cache coherency protocol. This intermediary state acts as a buffer that captures speculative cache accesses without allowing them to persist as permanent modifications, thereby blocking the attack path while preserving speculative execution functionality

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If cache state changes are allowed during speculative execution, then productivity is improved, but reliability is worsened due to information leakage

Engineering Contradiction:

Improvespeculative execution performanceVSAvoidinformation security

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic state transitions in the cache coherency protocol where cache lines can transition to speculative-modified state during speculative execution, and then either commit to modified state or revert to invalid state based on speculation outcome. This dynamic approach allows flexible handling of speculative accesses while ensuring security through proper state management

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms through the cache coherency protocol that monitor speculative execution outcomes and adjust cache states accordingly. When speculation is confirmed correct, cache lines transition from speculative-modified to modified state; when speculation fails, they revert to invalid state, providing feedback-based security control

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11231931B1Mechanism for mitigating information leak via cache side channels during speculative execution

Publication Date: 2022.01.25 ADVANCED MICRO DEVICES INC

AI summary

A processor includes a first core and a second core to execute computer instructions. Each of the cores includes its own private memory cache and speculative load queue. The speculative load queue stores cachelines for the computer instructions and data when the core is operating in a speculative state with respect to a process or thread. The processor includes a state tracking buffer having a state field to store a speculative exclusive ownership state for each cacheline in the speculative load queue when present therein.