Speculative Memory Move via Cache State Machines
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Solution Overview
Problem
In RISC processor architectures, memory moves consume architected registers for an extended duration, leading to inefficiencies and decreased performance due to the need for load-store instruction pairs, which limits the availability of these scarce resources for other instructions.
Innovation Solution
Implementing copy and paste functionality, where a lower-level cache allocates state machines to service copy-type and paste-type requests, allowing speculative reading and writing of data granules, and using barrier requests to order memory access requests, thereby reducing the pressure on architected registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load-store instruction pairs are used to perform memory moves in RISC architecture, then data can be moved between memory locations, but architected registers are occupied for extended durations reducing availability for other instructions
Solution Approach 1:
The patent segments the memory move operation into multiple granule-sized chunks, processing them in parallel through multiple state machines. This allows the memory move to be divided into independent units that can be handled concurrently, reducing the time each register is occupied and improving overall throughput.
Solution Approach 2:
The patent introduces a new dimension of parallelism by allocating multiple state machines (first state machine, second state machine, third state machine) to handle different granules simultaneously. This multi-dimensional approach allows concurrent processing of multiple memory granules, effectively increasing processor productivity without proportionally increasing register occupation time.
2Productivity
If multiple state machines are allocated to service copy-type and paste-type requests speculatively, then memory move throughput is improved, but cache complexity increases
Solution Approach 1:
The patent implements speculative execution by allocating state machines and buffers in advance before the actual memory move is confirmed. The lower level cache speculatively services copy-type and paste-type requests by pre-allocating resources, and only commits the operation if validation succeeds. This preliminary action improves throughput by avoiding sequential processing while managing complexity through controlled speculation.
Solution Approach 2:
The patent introduces non-architected buffers as intermediary storage between the lower level cache and the destination memory location. These buffers temporarily hold granules during the speculative memory move operation, acting as mediators that decouple the cache complexity from the register pressure while enabling parallel processing through multiple state machines.
3Reliability
If barrier requests are processed to ensure ordering of memory accesses, then memory consistency is maintained, but processing delay increases
Solution Approach 1:
The patent implements dynamic barrier handling by allowing memory moves to proceed speculatively through multiple state machines while maintaining the ability to enforce ordering when barriers are encountered. The system dynamically adjusts between speculative parallel execution and ordered sequential processing based on barrier presence, optimizing both reliability and time efficiency.
Data Source
AI summary
A lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed, as well as a barrier request that requests ordering of memory access requests prior to and after the barrier request. The barrier request precedes a copy-type request and a paste-type request of the memory move in program order. Prior to completion of processing of the barrier request, the lower level cache allocates first and second state machines to service the copy-type and paste-type requests. The first state machine speculatively reads a data granule identified by a source real address of the copy-type request into a non-architected buffer. After processing of the barrier request is complete, the second state machine writes the data granule from the non-architected buffer to a storage location identified by a destination real address of the paste-type request.