Speculative Message Interface Unit for Low Latency Data Networks

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Solution Overview

Problem

Existing message passing networks in data-intensive applications are inflexible, leading to high latency and low throughput due to FIFO requirements and the need for contiguous message grouping, which hinders efficient communication between processors and specialized processing blocks.

Innovation Solution

A message network interface unit that speculatively creates messages in scratchpad memory and queues them for later transmission, allowing for flexible message creation and prioritization, reducing processor clock cycles and latency by enabling message creation during idle periods and using priority queues for efficient message processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If messages are sent using traditional FIFO-based interfaces, then message ordering is maintained, but message latency increases and throughput decreases

Engineering Contradiction:
Improvemessage latencyVSAvoidmessage throughput
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent implements speculative message creation where the message interface unit proactively creates messages in scratchpad memory during processor idle periods, before they are actually needed. This preliminary action eliminates the waiting time for message creation, reducing latency while allowing parallel processing to maintain high throughput.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent divides the message creation and transmission process into separate stages: speculative creation in scratchpad memory, validation against actual needs, and selective transmission. This segmentation allows the system to prepare messages in advance without blocking the processor, improving both latency and throughput.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If messages are created speculatively in scratchpad memory, then message creation flexibility increases and latency decreases, but interface complexity increases

Engineering Contradiction:
Improvemessage creation flexibilityVSAvoidinterface complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a message interface unit as an intermediary between the processor and message network. This intermediary handles the complex speculative message creation logic in dedicated hardware (scratchpad memory and associated logic), keeping the processor simple while enabling flexible message creation. The intermediary absorbs the complexity rather than propagating it throughout the system.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If priority queues are implemented for message processing, then message prioritization improves and response time decreases, but device complexity increases

Engineering Contradiction:
Improvemessage processing speedVSAvoidqueue management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements priority queues with differentiated access rights where different processors or message sources can write to specific queues based on their priority level. This local quality approach allows high-priority messages to be processed faster without requiring complex global arbitration, as each queue operates independently with its own management logic.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP2568388B1Processor to message-based network interface using speculative techniques
Publication Date: 2017.03.15 ALTERA CORP
  • EP2568388B1 patent drawing
  • EP2568388B1 patent drawing
  • EP2568388B1 patent drawing

AI summary

Methods and systems are provided for a message network interface unit (a message interface unit), coupled to a processor, that is used for allowing the processor to send messages to a hardware unit. Methods and systems are also provided for a message interface unit, coupled to a processor, that is used for allowing a processor to receive messages from a hardware unit. The message network interface unit described herein may allow for the implementation data-intensive, real time applications, which require a substantially low message response latency and a substantially high message throughput.