Speculative Parsing for Integrated Circuit Layout Segmentation
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Solution Overview
Problem
Large integrated circuit layout design files require significant time to read and parse, hindering the efficiency of CAD tools, especially when dealing with large files in formats like OASIS or GDSII.
Innovation Solution
The segmentation of layout design data into contiguous regions allows for parallel processing by determining start locations within the file, using a speculative parsing method that estimates cell record starts and validates them, enabling efficient parsing across multiple CPUs or cores with minimal shared data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large integrated circuit layout design files are parsed sequentially by a single CPU, then parsing accuracy is maintained, but parsing time becomes excessively long
Solution Approach 1:
The patent divides large layout design files into multiple smaller segments that can be parsed in parallel by different CPU cores. Segment boundaries are determined by identifying cell definition records, ensuring each segment contains complete cell definitions. This segmentation enables parallel processing while maintaining parsing accuracy, directly resolving the contradiction between parsing speed and parsing time.
2Loss of time
If the file is divided into multiple segments for parallel processing, then parsing time is reduced, but determining accurate segment boundaries becomes complex
Solution Approach 1:
The patent performs preliminary scanning of the layout file to identify all cell definition records before actual parallel parsing begins. This preliminary action establishes segment boundaries in advance, allowing subsequent parallel processing to proceed without complex boundary determination logic. The complexity is front-loaded into a single preprocessing pass, simplifying the parallel parsing phase.
Solution Approach 2:
The segmentation process uses the file's own structure (cell definition records) to determine segment boundaries automatically. The parser identifies natural boundaries within the file format itself, eliminating the need for external segmentation tools or complex algorithms. The file structure serves its own segmentation needs, reducing overall system complexity.
3Productivity
If parallel parsing is implemented across multiple CPUs, then processing throughput increases, but coordination and data sharing between processors becomes difficult
Solution Approach 1:
By segmenting the file at cell definition boundaries, the patent ensures that each CPU core processes independent segments with no overlapping data requirements. This natural segmentation eliminates the need for complex inter-processor coordination, data locking mechanisms, or shared memory management, allowing simple parallel processing while maintaining high throughput.
Data Source
AI summary
A method of parsing integrated circuit layout design data. According to some implementations, the segment boundaries are designated by first identifying data in the integrated circuit layout design data that matches a cell record start value. Next, the subsequent data is parsed, until a threshold amount of subsequent data has been parsed without identifying another cell record start value. When the threshold amount of subsequent data has been parsed without identifying another cell record start value, the next data in the integrated circuit layout design data matching a cell record start value is designated as a segment boundary. Integrated circuit layout design data can be segmented sequentially, or by using dyadic division. Once the integrated circuit layout design data has been broken up into segments, the segments can be provided to a parallel processing computing system for parsing in parallel.