Speculative Program Counter Range Verification
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Solution Overview
Problem
Data processing architectures face inefficiencies in handling program counter modifications, particularly during branch instructions, as existing solutions require costly hardware modifications to provide predictive functionality for maintaining authorized program counter ranges, leading to potential delays in instruction execution.
Innovation Solution
An apparatus and method that utilize speculative execution of instructions based on predicted branch outcomes, maintaining a speculatively executed program counter range and verifying it against the permitted range upon resolution of the modification, allowing for continuous instruction execution without the need for predictive capability in program counter range indications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If branch prediction and speculative execution are used to improve instruction execution speed, then execution speed is improved, but hardware complexity increases due to required predictive functionality configuration
Solution Approach 1:
The patent applies preliminary action by pre-fetching instructions from predicted target addresses before branch resolution occurs. The fetch circuitry speculatively executes instructions based on predicted branch outcomes, allowing the processor to continue execution without waiting for branch resolution. This preliminary execution of instructions ahead of time improves execution speed while avoiding the need for complex predictive configuration of the instruction fetch unit.
2Reliability
If program counter range verification is performed after branch resolution to ensure security, then security is improved, but execution speed decreases due to verification delays
Solution Approach 1:
The patent applies skipping by temporarily bypassing program counter range verification during speculative execution. Instructions are fetched and executed speculatively without immediate verification of whether their program counter addresses fall within the authorized range. The verification is deferred until after branch resolution, at which point the speculatively executed instructions are either committed or discarded based on whether the predicted branch outcome was correct. This approach maintains security while minimizing verification delays during critical execution paths.
Data Source
AI summary
An apparatus and method of operating an apparatus are disclosed. The apparatus has a program counter permitted range storage element defining a permitted range of program counter values for the sequence of instructions it executes. Branch prediction circuitry predicts target instruction addresses for branch instructions. In response to a program counter modifying event, a program counter speculative range storage element is updated corresponding to each speculatively executed instruction after a branch instruction. Program counter permitted range verification circuitry is responsive to resolution of a modification of the program counter permitted range indication resulting from the program counter modifying event to determine whether the speculatively executed program counter range satisfies the permitted range of program counter values. A branch mis-prediction mechanism may support the response of the apparatus if the permitted range of program counter values is violated.