Speculative Vector Instruction Execution Mechanism

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Solution Overview

Problem

Conventional processors that process vector instructions with predication face inefficiencies due to the need to wait for predicate vectors to become available, leading to increased latencies and adverse effects on performance.

Innovation Solution

A processor mechanism that allows the execution of vector instructions to begin when operands are available, even if the predicate vector is not available, with temporary storage of results until the predicate is ready, and subsequent updating of the destination vector upon predicate availability, while suppressing faults and re-initiating instructions as needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processor waits for the predicate vector to become available before executing the vector instruction, then the correctness of the predicated operation is ensured, but the execution latency increases and performance deteriorates

Engineering Contradiction:
Improvecorrectness of predicated operationVSAvoidexecution latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The processor executes the vector instruction preliminarily before the predicate vector is available, storing the results in a temporary holding unit. This preliminary execution allows the instruction to proceed without waiting for the predicate, reducing latency while maintaining correctness through later validation against the predicate vector.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A holding unit is introduced as an intermediary storage mechanism between the vector instruction execution and the predicate vector availability. This holding unit temporarily stores execution results, allowing the instruction to complete before the predicate is ready, while ensuring results are only committed to the destination when the predicate validates them.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If the processor initiates vector instruction execution as soon as operands are available, then execution speed improves, but faults may be raised incorrectly before predicate availability is confirmed

Engineering Contradiction:
Improveinstruction execution speedVSAvoidfault detection accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The processor performs preliminary execution of the vector instruction without waiting for the predicate vector, allowing speed improvement. Faults are suppressed during this preliminary phase and only checked after the predicate vector becomes available, ensuring accurate fault detection based on the actual predicate condition.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The processor preemptively suppresses faults that would otherwise be raised during preliminary execution before the predicate is available. This prevents incorrect fault detection while allowing the instruction to execute early, and faults are only re-evaluated when the predicate vector is ready to validate the execution context.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS9298456B2Mechanism for performing speculative predicated instructions
Publication Date: 2016.03.29 APPLE INC
  • US9298456B2 patent drawing
  • US9298456B2 patent drawing
  • US9298456B2 patent drawing

AI summary

A mechanism for executing speculative predicated instructions may include execution of initiating execution of a vector instruction when one or more operands upon which the vector instruction depends are available for use, even if a predicate vector that the vector instruction also depends is not available. If the predicate vector was not available, the results of the execution of the vector instruction may be temporarily held until the predicate vector becomes available, at which time, a destination vector may be updated with the results.