Speed Converting Unit for High-Speed Semiconductor Testing
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Solution Overview
Problem
High-speed semiconductor device testing requires high-speed testers, leading to increased costs and complexity, particularly in detecting failures due to the need for sophisticated built-in self-test circuits and multiple input/output terminals, which complicates the detection of internal circuit failures.
Innovation Solution
A semiconductor device and test system that serially input and output test pattern data at different speeds using a speed converting unit and feed-through path, allowing for high-speed testing with a low-speed tester by bypassing internal circuits and using fewer input/output terminals, thereby reducing testing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-speed tester is used to test high-speed semiconductor devices, then test speed and accuracy are improved, but testing cost increases
Solution Approach 1:
A speed converting unit is introduced as an intermediary component between the low-speed tester and the high-speed semiconductor device. This unit converts the low-speed test signal into a high-speed signal, enabling accurate testing of high-speed devices without requiring an expensive high-speed tester. The speed converting unit acts as a mediator that bridges the speed mismatch between the tester and the device under test.
2Ease of manufacture
If built-in self-test circuits are used to test high-speed devices with low-speed testers, then testing cost is reduced, but device complexity increases
Solution Approach 1:
The testing functionality is extracted from the semiconductor device itself and placed in an external speed converting unit. Instead of embedding complex BIST circuits within the device, the patent uses an external unit that performs the speed conversion function. This extraction reduces the device complexity while maintaining the ability to test high-speed devices with low-speed testers.
3Productivity
If SERDES scheme is used to convert parallel low-speed data to serial high-speed data, then testing capability is improved, but the number of terminals required increases
Solution Approach 1:
The patent merges the functions of multiple terminals into a single serial terminal. Instead of using multiple parallel terminals for data input and output, the speed converting unit combines these functions into a single serial interface. This merging reduces the number of terminals required while maintaining the ability to perform high-speed testing through serial data transmission.
4Reliability
If multiple input and output terminals are used for testing, then test coverage is improved, but ease of operation deteriorates
Solution Approach 1:
Instead of using multiple terminals to achieve test coverage, the patent inverts the approach by using a single terminal with speed conversion. The serial interface with speed converting unit provides the same test coverage as multiple parallel terminals would, but with simpler operation and fewer connections required. This inversion simplifies the testing process while maintaining comprehensive test coverage.
Data Source
AI summary
Provided are a semiconductor device, a test board, and a test system and method for testing a semiconductor device. The semiconductor device includes an input terminal to which test pattern data is serially input at a first speed and an output terminal which one-to-one corresponds to the input terminal and serially outputs the test pattern data to the outside at a second speed that is different from the first speed.