Speed Units for High-Speed Serial Data Communication
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Solution Overview
Problem
Current serial data communication methods between a master device and multiple slave drive units for peripheral devices are limited by slow data transfer rates, typically operating at 1 MHz, which results in inefficiencies and pin shortages, especially in applications like the automotive field where more devices are needed.
Innovation Solution
Implementing a method and apparatus that utilizes individual speed units with serial shift registers and multiplexor logic to enable serial data communication at a faster pulse rate (20 MHz) in a series chain and duplex data communication at a slower pulse rate (1 MHz) between the master device and slave drive units, allowing for parallel data transfer between the speed units and slave drive units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard SPI communication is used with slave devices operating at 1 MHz, then reliable data communication is achieved, but the data transfer rate is slow and pin availability is insufficient
Solution Approach 1:
The system is divided into master device, slave drive units, and speed units with separate functions. The speed units handle high-speed data buffering while slave drive units maintain reliable communication at 1 MHz, separating the reliability function from the speed function to resolve the contradiction between reliable communication and fast transfer rate
Solution Approach 2:
Speed units act as intermediary buffer devices between the master device and slave drive units. They receive data at high speed from the master device, then transfer it at the slower 1 MHz rate to the slave drive units, mediating the speed mismatch and enabling both fast overall transfer and reliable slave communication
2Quantity of substance
If more peripheral slave devices are connected in parallel to the bus, then device coverage is increased, but pin availability on the master device is exhausted
Solution Approach 1:
The system transitions from a traditional parallel bus architecture to a hierarchical structure with multiple communication dimensions: high-speed serial communication between master and speed units, and low-speed serial communication between speed units and slave drive units. This dimensional change allows many more devices to be connected without requiring additional pins on the master device
3Quantity of substance
If data is transferred sequentially to each of the five slave devices at 1 MHz, then complete data coverage is achieved, but the overall cycle time is 40 µS
Solution Approach 1:
The speed units perform preliminary high-speed data reception and buffering before the actual transfer to slave drive units begins. This preliminary action at 20 MHz allows the system to prepare data in advance, reducing the overall cycle time from 40 µS to 10 µS while maintaining complete data coverage across all five slave devices
Data Source
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AI summary
A microcontroller (MC) is provided with a plurality of slave drive units (D1-D5) for driving peripheral devices. Individual speed units (SU1-SU5) are provided which have a serial shift register, multiplexors (MU1-MU2), and a duplex data communication connection via pins (LSSI, LSSO) with individual serial registers of a connected slave drive unit. A serial data connection via pins (HSSI, HSSO) is provided between the serial registers of the speed units to form a series chain connection with a data input at one end of the chain and a data output at the other end of the chain. The multiplexors have logic for enabling, in a first cycle or mode, the serial data connection between the serial shift registers of the speed units whereby data is serially communicated, at a first relatively faster pulse rate, from a pin (MOSI) of the microcontroller into the data input of the series chain and to a pin (MISO) of the microcontroller from the data output of the series chain. The multiplexors have logic for enabling, in a second cycle or mode for each and every pair of a single speed unit and a corresponding slave drive unit, the duplex data communication between the serial shift registers of the pair, at a second relatively slower pulse rate, whereby data can be serially communicated in parallel therebetween at a second relatively slower pulse rate.