SPHINCS+ Signature Verification Circuitry Latency Reduction

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Solution Overview

Problem

Classical digital signature schemes like DSA, RSA, and ECDSA are vulnerable to attacks by quantum computers, necessitating the development of quantum-resistant digital signature methods.

Innovation Solution

The implementation of the SPHINCS+ algorithm in signature verification circuitry, optimized for reduced latency and area usage, using SHAKE256 hash function and parallelized memory operations to achieve quantum security.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If quantum-resistant signature algorithms (SPHINCS+) are implemented, then security against quantum computer attacks is improved, but computational complexity and processing time increase

Engineering Contradiction:

Improvequantum resistanceVSAvoidverification latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The verification process is divided into multiple parallel stages: signature parsing, public key validation, and hash computation. Each stage processes independent components (FORS trees, hypertrees, WOTS+ chains) simultaneously using separate computational units, reducing overall verification latency while maintaining quantum-resistant security.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential software-based verification to parallel hardware-based verification using a field-programmable gate array (FPGA). This dimensional shift from temporal processing to spatial parallelism achieves approximately 184× latency reduction while preserving the cryptographic security properties of SPHINCS+.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If hardware-based verification circuitry is used, then verification speed is improved, but device area and complexity increase

Engineering Contradiction:

Improveverification speedVSAvoidcircuitry area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent employs a reconfigurable FPGA architecture that dynamically allocates hardware resources based on the specific verification requirements. The circuitry can be reprogrammed to optimize for different parameter sets (e.g., varying tree heights, hash function configurations), achieving high verification speeds without permanently dedicating excessive hardware area.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The verification circuitry is designed with universal components that can handle multiple operations: parsing different signature formats, validating various tree structures (FORS, hypertrees), and computing multiple hash functions. This multi-functionality reduces the total hardware area required compared to dedicated circuits for each operation.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240223381A1Post-quantum cryptography signature verification

Publication Date: 2024.07.04 ALTERA CORP

AI summary

Techniques for performing digital signature verification are described. Digital signature verification circuitry includes a memory; and signature verification circuitry, including Secure Hash Algorithm (SHA) circuitry; message representative generator circuitry; tree verification circuitry; and hypertree verification circuitry.