SPI Slave Auto-Increment Register Addressing

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Solution Overview

Problem

The existing SPI communication interface is inefficient due to the need to transmit a start register address at the beginning of each frame, which creates overhead and reduces data transmission efficiency, especially for multi-frame operations.

Innovation Solution

The implementation of a slave device with a data register configured to automatically increment its register address across chip select frames based on configuration information, allowing for continuous data read or write operations without the need for repeated start register address transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the master transmits a start register address at the beginning of each SPI communication frame, then the slave device can correctly identify the starting register for data read/write operations, but this creates communication overhead and reduces data transmission efficiency

Engineering Contradiction:
Improveregister address identification accuracyVSAvoiddata transmission efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The slave device performs preliminary action by maintaining and automatically incrementing the register address pointer between consecutive SPI communication frames. The slave device stores the current register address in an internal register and automatically increments it after each frame's data transfer, so that when the next frame arrives, the address is already prepared. This eliminates the need for the master to transmit the start register address in each frame, resolving the contradiction by preserving address identification accuracy while improving transmission efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The slave device serves itself by autonomously managing its own register address pointer. The slave device automatically updates its internal address register based on the data transfer completion status and pre-configured increment values, without requiring external commands from the master device. This self-service mechanism eliminates the overhead of repeated address transmissions while ensuring accurate register identification for each frame.

Inventive Principle:
Principle #25Self-service

2Measurement precision

If the master transmits the start register address for each read operation in every SPI communication frame, then the slave device can accurately locate the data source, but 25% of each frame is lost for addressing purposes

Engineering Contradiction:
Improvedata source location accuracyVSAvoidusable data transmission capacity
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The slave device performs preliminary action by pre-calculating and storing the next register address in an internal pointer register before the SPI frame arrives. The address increment is computed in advance based on the previous transfer's end position and the configured increment value. This preliminary preparation ensures that when the frame arrives, the address is already ready, eliminating the need to waste frame bandwidth on address transmission while maintaining accurate data source location.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

An internal address pointer register in the slave device acts as an intermediary between the data transfer operation and the register address space. This intermediary automatically updates its value based on transfer completion and configuration, mediating the address selection process without requiring external communication. This eliminates the need to transmit addresses in each frame while ensuring accurate data source identification.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Duration of action of moving object

If sequential read/write operations are performed using multiple SPI communication frames, then continuous data transfer is achieved, but repeated address transmission increases communication overhead

Engineering Contradiction:
Improvecontinuous data transfer capabilityVSAvoidcommunication protocol complexity
Core Design Contradiction:
Duration of action of moving objectVSDevice complexity

Solution Approach 1:

The slave device maintains continuity of useful action by automatically maintaining its register address pointer across multiple consecutive SPI communication frames. The address pointer persists in the slave's internal memory and is automatically incremented between frames, allowing seamless continuous data transfer without interrupting the data flow for address re-transmission. This enables uninterrupted sequential read/write operations while eliminating the complexity of repeated address setup.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The slave device performs self-service by autonomously managing its address pointer state across multiple frames. The slave automatically detects frame completion, updates its internal address register with the next target address, and prepares for the subsequent frame without external intervention. This self-managed address progression simplifies the communication protocol by removing the need for repeated address transmission while maintaining continuous data transfer capability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11630796B2Serial peripheral interface (SPI) automatic register address incrementation across data frames
Publication Date: 2023.04.18 INFINEON TECHNOLOGIES AG
  • US11630796B2 patent drawing
  • US11630796B2 patent drawing
  • US11630796B2 patent drawing

AI summary

A serial peripheral interface (SPI) communication system includes a memory configured with a start register address and an end register address that define a register address range for a data operation; a chip select terminal configured to receive a chip select signal comprising an active and idle signal levels that define a plurality of chip select frames; a serial data input terminal configured to receive a master out, slave in (MOSI) signal, wherein the MOSI signal includes configuration information received in a first chip select frame of the data operation, wherein the configuration information includes an operation command bit indicating whether the data operation is a write operation or a read out operation and an auto-incrementation control bit indicating whether automatic register address incrementation across chip select frames is enabled or disabled; and a serial data output terminal configured to transmit a master in, slave out (MISO) signal.