Hardware Accelerated SPI Automatic Read Control System

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing systems face challenges in reading data from sensors like gyroscopes and optical flow meters in real-time due to frequent software interrupts, which affect software efficiency and real-time processing.

Innovation Solution

A hardware-based automatic read control system for SPI interfaces, incorporating an SPI module, APB module, DMA controller, state machine controller, and buffers, that schedules data reading in batches with precise timing to reduce CPU interrupts and improve processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is read frequently by triggering software interrupts, then real-time processing requirement is met, but software execution smoothness is affected and software efficiency is reduced

Engineering Contradiction:
Improvereal-time processingVSAvoidsoftware efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces a state machine controller as an intermediary hardware component that mediates between the SPI interface and the CPU. This state machine automatically manages data reading from sensors, buffer management, and timing control, eliminating the need for frequent software interrupts while ensuring real-time data acquisition. The intermediary hardware layer handles the time-consuming operations, allowing the CPU to focus on higher-level processing tasks.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the software-based data reading mechanism with a hardware-based state machine controller. By implementing the data reading logic in hardware rather than software, the system achieves real-time processing without the overhead of software interrupts. The hardware state machine executes data acquisition tasks in parallel with CPU operations, substituting the sequential software execution model with concurrent hardware operation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Speed

If data is read frequently, then real-time sensor data is obtained, but frequent interrupts affect the smoothness of software execution

Engineering Contradiction:
Improvedata read frequencyVSAvoidsoftware execution smoothness
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The patent segments the data reading function into independent hardware modules: a state machine controller for sequencing, buffers for data storage, and a DMA controller for data transfer. This segmentation allows data reading to occur continuously at high frequency through hardware operations, while the CPU is only invoked when data is ready in the buffer, thus maintaining software execution smoothness while achieving frequent data acquisition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by having the hardware state machine and buffers prepare data for reading before the CPU needs it. The state machine continuously monitors sensor data and pre-loads it into buffers using DMA transfers, so that when the CPU requires data, it is already available without triggering interrupts. This preliminary data preparation ensures both high read frequency and smooth software execution.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11734219B2Automatic read control system based on a hardware accelerated SPI and automatic read control method
Publication Date: 2023.08.22 AMICRO SEMICONDUCTOR CO LTD
  • US11734219B2 patent drawing
  • US11734219B2 patent drawing

AI summary

Disclosed is a hardware acceleration based automatic read control system and method for a serial peripheral interface (SPI). The automatic read control system includes an SPI module, an advanced peripheral bus (APB) module, an interrupt generation module, a direct memory access (DMA) controller, a state schedule control module, a register group module, a count signal generation module, a transmitted data buffer and a received data buffer; the state schedule control module, the register group module and the count signal generation module form a state machine system; and the state schedule control module controls automatic timed batch read of sensor data of the SPI according to configuration information of the register group module and counting and timing information of the count signal generation module.