SPI Buffer Stage with Dual Modules for Fast Low-Power Switching
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Solution Overview
Problem
Conventional buffer stages in CMOS systems face a trade-off between switching speed and power consumption, particularly due to short-circuit currents during transitions, which impact both the 'fan-out' capability and access time in high-frequency SPI bus communications.
Innovation Solution
A buffer stage device with dual buffer modules, one optimized for fast switching during dynamic data transmission and another for low current consumption during static phases, using transistors with different on-state impedances to manage transitions and minimize short-circuit currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the on-state impedance of transistors is reduced to increase fan-out and decrease access time, then switching speed is improved, but short-circuit current during transitions increases
Solution Approach 1:
The patent applies dynamics by making the transistor impedance adjustable rather than fixed. The first transistor has a first impedance value optimized for fast switching, while the second transistor has a second impedance value optimized for low power consumption. The system dynamically selects which transistor to activate based on whether fast switching or low power consumption is the priority, resolving the contradiction between switching speed and power loss.
Solution Approach 2:
The patent changes the impedance parameter of transistors to resolve the contradiction. By providing transistors with different impedance values (first impedance for speed, second impedance for power efficiency) and selecting the appropriate transistor based on operational requirements, the system achieves both fast switching and low power consumption at different times, rather than being constrained by a single fixed impedance value.
2Loss of energy
If anti-collision assembly is used to prevent short-circuit current, then power consumption is reduced, but switching time increases
Solution Approach 1:
The patent uses dynamics by providing two different transistor configurations with different impedance values and dynamically selecting which one to use. When fast switching is needed, the first transistor with lower impedance is activated despite higher power consumption risk. When power conservation is priority, the second transistor with higher impedance is used. This dynamic selection resolves the contradiction between power consumption and switching time.
Solution Approach 2:
The patent segments the buffer stage into two separate transistors (first transistor and second transistor) with different characteristics. Instead of using a single transistor with compromise characteristics or a complex anti-collision assembly, the buffer is divided into multiple specialized components, each optimized for a specific function (speed or power efficiency), and the appropriate segment is activated based on operational needs.
Data Source
AI summary
In some embodiments, a buffer stage device includes a data input for receiving a data signal, a clock input for receiving a clock signal, a data output and a processor that is configured to deliver, to the data output, the data from the data signal in synchronism with clock cycles of the clock signal. The processor includes a first buffer module configured to deliver, to the data output, each datum in synchronism with a first edge of the clock signal and during a first half of a clock cycle, and a second buffer module configured to hold the datum at the data output during the second half of the clock cycle.