SPI Bus Switch for Flash Memory Controller Priority Management
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Solution Overview
Problem
In computer systems, existing memory control devices for SPI flash memory struggle to efficiently manage access priority and sharing between primary and secondary controllers, leading to potential timing violations and reduced system performance due to continuous access by the primary controller, which prevents the secondary controller from accessing the flash memory.
Innovation Solution
A memory control device with a bus switch that selectively couples SPI buses between primary and secondary controllers, including a bus share regulation unit and interrupt mechanism to manage access priority and prevent prolonged access by the primary controller, ensuring fair sharing and timely access by the secondary controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the primary controller continuously accesses the flash memory, then the primary controller's access speed is improved, but the secondary controller cannot access the flash memory and timing violations occur
Solution Approach 1:
The bus switch is pre-configured with switching signals that are generated in advance based on access request patterns. When the primary controller initiates a long-duration access, the system preemptively switches the bus to the secondary controller after a predetermined time interval, ensuring timing compliance before violations occur. This preliminary switching action prevents the primary controller from monopolizing the bus indefinitely.
Solution Approach 2:
The system implements periodic switching between primary and secondary controllers through a timing mechanism that generates switching signals at regular intervals. This periodic action ensures that neither controller can continuously occupy the bus, maintaining timing compliance while allowing both controllers to access the flash memory in alternating periods. The switching frequency is adjusted based on access duration requirements.
2Productivity
If the primary controller monopolizes the SPI bus, then the primary controller's productivity is improved, but the secondary controller experiences access delays and system performance deteriorates
Solution Approach 1:
The bus switching mechanism dynamically adjusts the allocation of bus access time between primary and secondary controllers based on real-time access patterns and requirements. The system monitors access duration and automatically switches the bus connection, allowing the primary controller to utilize the bus extensively when needed while guaranteeing periodic access opportunities for the secondary controller. This dynamic time-sharing approach optimizes overall system productivity while preventing excessive wait times for either controller.
3Device complexity
If a simple bus sharing mechanism is used, then the device complexity is reduced, but access priority management and timing control become inadequate
Solution Approach 1:
The bus switch serves as an intermediary device between the primary controller, secondary controller, and flash memory. It incorporates intelligent switching logic that automatically manages access priority and timing without requiring complex coordination protocols between controllers. The switching unit responds to timing signals and access requests, making priority management transparent to the controllers while maintaining simple physical connections. This intermediary approach balances device complexity with operational ease.
Data Source
AI summary
A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal.