SPI Chip Control for GPIO-Free Status Synchronization

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Solution Overview

Problem

Existing methods for communication between System-on-a-Chip (SOC) chips using SPI are unreliable for status synchronization, particularly in dual-core heterogeneous systems, as they rely on additional GPIO signals which are inflexible and resource-consuming, and are not suitable for chip initialization stages.

Innovation Solution

Utilizing the characteristic of an SPI slave's first-in-first-out memory to repeat a previous transmission word when empty, allowing status synchronization through SPI bus resources without additional GPIO signals, ensuring reliable protocol interaction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional GPIO signals are used for status synchronization, then reliability of communication is improved, but device complexity and hardware resource consumption increase

Engineering Contradiction:

Improvecommunication reliabilityVSAvoidhardware resource consumption

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the SPI bus serve multiple functions: both data transmission and status synchronization. By utilizing the existing SPI communication channel for status queries and responses, the system eliminates the need for separate GPIO signals, thereby reducing hardware complexity while maintaining communication reliability through the same reliable SPI protocol

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the status synchronization function with the existing data communication function over the SPI bus. Instead of having separate dedicated lines for status indication, the system combines status information transmission with the regular data exchange protocol, reducing the number of physical signals required while maintaining reliable status awareness

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If additional GPIO signals are used for status synchronization, then reliability of communication is improved, but ease of manufacture decreases

Engineering Contradiction:

Improvecommunication reliabilityVSAvoidchip design flexibility

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The SPI bus is designed to perform multiple functions including both data transmission and status synchronization. This multi-functionality approach simplifies chip design by eliminating the need for separate GPIO pins, reducing the number of electrical connections that need to be designed and manufactured, thereby improving ease of manufacture while maintaining reliability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent extracts the status synchronization function from the physical layer (separate GPIO signals) and moves it to the protocol layer (SPI communication). By taking out the status indication from dedicated hardware lines and implementing it through the existing SPI protocol mechanism, the system maintains reliability while simplifying the physical design and manufacturing process

Inventive Principle:

Principle #2Taking out (Extraction)

3Device complexity

If traditional SPI communication is used without status query mechanism, then device complexity is reduced, but reliability of status synchronization deteriorates

Engineering Contradiction:

Improvehardware resource consumptionVSAvoidstatus synchronization reliability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the slave device responds to status query signals from the master device. The slave device transmits status information back to the master through the SPI bus, enabling reliable status synchronization. This feedback approach maintains low hardware complexity by using the existing bidirectional SPI communication for status exchange

Inventive Principle:

Principle #23Feedback

4Ease of operation

If status query mechanism is implemented through SPI, then ease of operation is improved, but communication time increases

Engineering Contradiction:

Improvestatus synchronization reliabilityVSAvoidcommunication time

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The patent implements periodic status queries where the master device sends status query signals at appropriate intervals during the communication process. This periodic querying mechanism ensures reliable status synchronization without requiring continuous communication, thereby minimizing the time overhead while maintaining ease of operation through the established SPI protocol

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS20250307199A1Method, apparatus, electronic device, and storage medium for chip control

Publication Date: 2025.10.02 BEIJING ZITIAO NETWORK TECH CO LTD

AI summary

The present disclosure provides a method, an apparatus, an electronic device and a storage medium for chip control. The method is applied at a first chip in communication connection with a second chip through SPI. The method includes: transmitting a status query signal to the second chip through the SPI; receiving a first signal transmitted by the second chip through the SPI, and in response to the first signal being a first preset status signal, transmitting first transmission data to the second chip through the SPI; after finishing transmitting the first transmission data to the second chip through the SPI, retransmitting the status query signal to the second chip through the SPI; and receiving a second signal returned by the second chip through the SPI, and determining a status of the second chip according to the second signal.