SPI Slave Clock Path Using Schmitt Triggers for Low Loop Delay
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Solution Overview
Problem
Prior art SPI slave designs fail to meet the loop delay requirement for maximum SPI communication speed, especially at high frequencies and when thick oxide devices are used, due to increased delays in the data transmission path.
Innovation Solution
A slave device design that directly routes the serial clock signal to Schmitt triggers within the data sampling circuitry, allowing selective sampling of data at either the rising or falling edge of the clock signal, reducing loop delay by eliminating unnecessary level shifting and multiplexer switching delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the SCK signal is routed through level shifters and multiplexers to the clock input of the flip flop, then the slave can operate with thick oxide devices and underdriven transistors, but the loop delay increases and maximum SPI communication speed cannot be achieved
Solution Approach 1:
The patent segments the clock signal path by creating separate direct and indirect routes. The SCK signal is divided into two paths: one that goes directly to the data sampling circuitry (bypassing level shifters and multiplexers) and another that goes through the traditional level shifter and multiplexer path. This segmentation allows the critical clock path to be optimized for speed while other paths can maintain compatibility with thick oxide devices.
Solution Approach 2:
The patent introduces an intermediary buffer or direct routing mechanism that mediates between the SCK pad and the data sampling circuitry. This intermediary path eliminates the need for the SCK signal to pass through level shifters and multiplexers, thereby reducing propagation delay while still allowing those components to exist in the system for other signal paths that require thick oxide device compatibility.
2Adaptability or versatility
If the SCK signal passes through level shifters and multiplexers, then voltage domain compatibility is achieved, but the loop delay exceeds the requirement for high frequency full duplex communication
Solution Approach 1:
The patent segments the signal paths by creating a dedicated direct path for the SCK signal that bypasses voltage domain translation components, while other data signals continue to use the traditional path with level shifters. This allows the clock path to operate at high speeds for high frequency communication while other paths maintain voltage domain compatibility.
Solution Approach 2:
The patent applies different quality characteristics to different parts of the signal path. The critical clock path is optimized for speed with direct routing and minimal components, while other non-critical paths maintain full voltage domain compatibility through level shifters and multiplexers. This local optimization allows the system to achieve both high speed and adaptability in different locations.
3Loss of time
If unnecessary level shifting and multiplexer switching are eliminated, then loop delay is reduced to 6.4 ns, but the complexity of the data sampling circuitry increases
Solution Approach 1:
The patent merges the clock signal reception and data sampling functions into a unified data sampling circuitry block. By combining these functions, the circuit can directly sample data on the SCK signal edges without requiring separate level shifting and multiplexing stages, thereby reducing loop delay while consolidating circuit complexity into a single optimized block rather than distributing it across multiple components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new design achieves a loop delay of 6.4 ns, meeting the SPI standard for high frequency full duplex communication, even with thick gate oxides and underdriven transistors, enabling faster data transmission.
Implementation Method 1
The data sampling circuitry includes a first Schmitt trigger configured to selectively generate a clock pulse in response to a rising edge of the serial clock
Implementation Method 2
a first flip flop clocked by the clock pulse from the first Schmitt trigger and configured to receive the output data
Data Source
AI summary
A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.