SPI Clock Phase Delay for High-Rate DDR Data Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing serial peripheral interface (SPI) communication between a master device and a slave device faces significant delays due to the synchronization of clock signals, leading to difficulties in achieving high data transmission rates, especially in double data rate (DDR) mode, where frequencies above 100 MHz are challenging to maintain.
Innovation Solution
A clock control device and method that includes a local delay module, clock selector, and first delay module to adjust and synchronize clock signals, compensating for delays in the transmission path, allowing for accurate data sampling without reducing data transmission frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the master device uses the same clock signal as the slave device for data acquisition, then the system maintains simple clock synchronization, but the data transmission frequency must be reduced to a very low level to ensure correct data acquisition
Solution Approach 1:
The patent applies preliminary action by introducing a delay to the clock signal in advance before it reaches the master device. The delay module pre-adjusts the clock signal timing to compensate for transmission delays, allowing the master device to sample data at the correct moment without reducing transmission frequency. This proactive timing adjustment resolves the contradiction between maintaining simple synchronization and achieving high data transmission rates.
2Reliability
If the data transmission frequency is reduced to a very low level, then the master device can acquire correct data without complex delay compensation, but the communication efficiency and transmission rate are severely limited
Solution Approach 1:
The patent introduces a delay module as an intermediary component between the clock signal source and the master device. This intermediary actively adjusts the clock signal timing to match the data arrival time at the master device, ensuring accurate data acquisition while allowing high transmission frequencies. The delay module acts as a mediator that reconciles the timing mismatch without requiring frequency reduction, thus maintaining both reliability and productivity.
3Ease of operation
If the clock signal passes through the output path of the master device, the circuit transmission path between master and slave devices, and the input path of the master device, then the clock signal reaches the slave device for data driving, but significant delays are introduced that increase the delay difference between received data signal and output clock signal
Solution Approach 1:
The patent applies preliminary anti-action by introducing a compensatory delay to the clock signal that counteracts the transmission delays. The delay module pre-adjusts the clock signal timing to anticipate and offset the delays that will occur as the signal passes through the output path, transmission path, and input path. This proactive compensation reduces the net delay difference between the clock signal and data signal, resolving the contradiction between ease of operation and time loss.
Data Source
Figure 1A~1B
Figure 2~4
Figure 5A~5D
AI summary
A clock control device and a clock control method for a serial peripheral interface are disclosed. The clock control device is disposed in a control device and includes: a local delay module configured to delay a local clock signal to obtain a first delayed local clock signal; a clock selector configured to select one of the first delayed local clock signal and an external clock signal as a basic clock signal; and a first delay module configured to phase-delay the basic clock signal to obtain a delayed basic clock signal that can be used by the control device as a reception operating clock for sampling an external data signal transmitted by a storage device.