SPI Clock Delay Tuning for Temperature-Stable DDR Flash Reads
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Solution Overview
Problem
Existing System on a Chip (SoC) designs face challenges in maintaining reliable communication with DDR flash memory due to temperature variations, as the programmed tuning points for SPI interfaces become unsuccessful as operating temperatures change, leading to unreliable data programming and reading.
Innovation Solution
A method to select an SPI tuning point that includes determining maximum and minimum values for transmit and receive clock delays and reference clock cycles, identifying boundaries of unsuccessful regions, and choosing a tuning point that maintains successful operations over a wider range of temperatures by selecting the point farther from these boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If fixed SPI tuning points are programmed during manufacturing, then the communication interface can be initialized quickly, but the communication reliability deteriorates when operating temperatures change
Solution Approach 1:
The patent implements dynamic tuning point selection by determining multiple candidate tuning points corresponding to different operating temperature ranges, then selecting the appropriate tuning point based on actual operating conditions. This allows the SPI interface to adapt its timing parameters dynamically, maintaining reliable communication across temperature variations while keeping initialization efficient through pre-calculated candidate points.
Solution Approach 2:
The patent changes the timing parameters (tunin g points) of the SPI interface based on operating temperature ranges. By determining candidate tuning points with different clock delay values and selecting the appropriate one based on temperature, the system maintains optimal communication reliability without requiring extensive re-initialization, thus resolving the contradiction between quick initialization and temperature-dependent reliability.
2Reliability
If multiple candidate tuning points are determined and stored, then communication reliability across temperature ranges is improved, but device complexity increases
Solution Approach 1:
The patent segments the operating temperature range into multiple discrete temperature ranges, each associated with a specific candidate tuning point. This segmentation approach allows the system to store a limited set of pre-determined tuning points rather than continuous parameter sets, reducing storage requirements and selection complexity while maintaining reliability across the full temperature spectrum.
Solution Approach 2:
The patent performs preliminary determination of candidate tuning points during manufacturing or initialization, storing them for later use. This preliminary action eliminates the need for complex real-time calculations during operation, reducing runtime complexity while ensuring reliable communication by having pre-validated tuning points ready for selection based on measured temperature.
3Productivity
If tuning points are optimized for a specific temperature range, then communication performance is maximized in that range, but adaptability to other temperature ranges deteriorates
Solution Approach 1:
The patent creates a universal tuning point selection mechanism that determines multiple candidate tuning points covering different operating temperature ranges. The system can universally apply the same selection logic across various temperature conditions, allowing a single SPI interface to maintain optimal performance across diverse thermal environments rather than being specialized for one temperature range.
Solution Approach 2:
The patent implements dynamic adaptation by selecting different tuning points based on the current operating temperature range. This dynamic approach allows the system to maintain high communication performance across varying temperatures, transforming a static, temperature-specific optimization into a dynamic, temperature-adaptive solution that preserves productivity while enhancing adaptability.
Data Source
AI summary
A device and method are presented. Largest and smallest successful values of a receive clock delay and a transmit clock delay are determined. A first set of parameters for an SPI coupled to a DDR flash memory are set, including the largest successful values of the transmit clock delay and the receive clock delay, and a first value of a RD cycle. A second set of parameters for the SPI are set, including the smallest successful value of the transmit clock delay and receive clock delay, and a second value of the RD cycle. One of the first and second sets of parameters is selected based on whether the first or second set of parameters results in successfully reading from the DDR flash memory over a larger range of operating temperatures. The SPI is programmed using the selected one of the first and second sets of parameters.