SPI Controller Clock Halting for Variable Buffer Sizes
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Solution Overview
Problem
Conventional SPI data transmission requires SPI controllers with fixed buffer sizes to match the buffer sizes of SPI slaves, limiting the ability to control multiple SPI slaves with different buffer sizes and causing delays when the buffer is not fully filled during transmission.
Innovation Solution
Implementing a method where the SPI controller discontinuously provides a clock signal to the SPI slave, halting it between data transmission portions to refresh the buffer and restart it for subsequent transmissions, allowing the controller to manage multiple SPI slaves with varying buffer sizes by transmitting in smaller portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the SPI controller uses a fixed buffer size to match the SPI slave buffer size, then data transmission can be completed in one cycle, but the controller cannot manage multiple SPI slaves with different buffer sizes
Solution Approach 1:
The patent segments the data transmission process into multiple portions, allowing the buffer to be refilled between transmissions. The controller divides the data transmission into segments that can be sent in batches, with the buffer being replenished from the source during buffer halt periods, enabling flexible adaptation to different slave buffer sizes without requiring a fixed large buffer
Solution Approach 2:
The patent introduces dynamic buffer management where the buffer can be halted and refilled during data transmission. The system dynamically adjusts the transmission process by stopping the clock signal to halt the slave, refilling the buffer from the source, and then resuming transmission, allowing the same controller to adapt to various buffer size requirements of different slaves
2Productivity
If the chip select signal is disabled when the slave buffer is full to save transmission time, then transmission speed improves, but delays occur when the buffer is not fully filled
Solution Approach 1:
The patent applies preliminary action by refilling the buffer before the transmission cycle ends. Instead of waiting for the buffer to be completely full or the cycle to end, the system proactively refills the buffer during halt periods, ensuring that when transmission resumes, the buffer is ready to continue without delays
Solution Approach 2:
The patent maintains continuity of useful action by ensuring the buffer is continuously refilled during halt periods. The system eliminates idle time by keeping the buffer preparation process ongoing, so that when the clock signal resumes, data transmission can continue immediately without waiting for buffer refill, thus maintaining continuous productive action
3Reliability
If the buffer size is increased to match larger slave buffers, then complete data transmission in one cycle is enabled, but the controller cannot adapt to smaller buffer sizes of other slaves
Solution Approach 1:
The patent makes the controller universal by implementing a buffer management system that can adapt to slaves with any buffer size. Through dynamic halting and refilling mechanisms, the same controller configuration can efficiently serve multiple slaves with different buffer size requirements, eliminating the need for multiple specialized controllers
Data Source
AI summary
The invention provides a method for serial data transmission. First, a chip select signal is enabled to a device for serial data transmission. Data stored in a first buffer of a controller is then transmitted to a second buffer of the device. A clock signal is then halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the controller while the clock signal is halted. The clock signal is the restarted to operate the device after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating.