SPI Controller Register Update via DMA Mediator
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Solution Overview
Problem
Existing SPI controller technologies face challenges in achieving flexible configuration, compatibility, and continuous transmission speed, often prioritizing one aspect over the others, leading to inefficiencies in CPU resource utilization and register updates across multiple modules.
Innovation Solution
The proposed SPI controller includes an SPI clock signal generator, a register group for configuration storage, input/output controllers for data transfer, and an SPI state machine, coupled with a DMA controller for efficient configuration updates between transmissions, enabling flexible configuration, improved compatibility, and continuous transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CPU updates the SPI controller configuration between transmissions, then the SPI controller can switch between different operating configurations and maintain compatibility with various SPI devices, but the CPU overhead increases and transmission continuity is reduced due to long waiting time
Solution Approach 1:
The patent introduces a DMA controller as an intermediary between the CPU and SPI controller. The DMA controller receives configuration parameters from the CPU and automatically updates the SPI controller's register group, eliminating the need for CPU intervention during transmission. This mediator approach resolves the contradiction by allowing flexible configuration updates without burdening the CPU or interrupting transmission continuity.
Solution Approach 2:
The patent implements preliminary action by having the DMA controller pre-load configuration parameters and automatically update the SPI controller register group before each transmission begins. The configuration update occurs in advance during idle periods or between transmissions, so the SPI controller is already configured when needed, eliminating waiting time and maintaining transmission speed.
2Reliability
If the CPU updates the entire register group to ensure correct SPI transmission state, then transmission reliability is improved, but the CPU overhead and time consumption increase significantly
Solution Approach 1:
The patent extracts the register update function from the CPU and assigns it to the DMA controller. The DMA controller independently manages the configuration parameters and automatically updates only the necessary portions of the SPI controller register group, eliminating the time-consuming full register updates that previously required CPU intervention. This ensures transmission reliability while minimizing CPU time consumption.
Solution Approach 2:
The SPI controller is designed to be self-configuring through the DMA controller. The system automatically manages configuration updates without requiring CPU participation in each update cycle. The DMA controller monitors transmission states and performs register updates autonomously, allowing the system to maintain reliable operation while freeing the CPU for other tasks.
3Productivity
If multiple SPI transmissions are performed in sequence, then data throughput is improved, but the CPU overhead accumulates and affects overall system performance
Solution Approach 1:
The patent enables continuous SPI transmissions by having the DMA controller automatically manage the entire transmission sequence. Once the CPU initiates the first transmission and loads initial parameters, the DMA controller continuously manages subsequent transmissions without CPU intervention. This maintains high data throughput while eliminating the cumulative CPU overhead that would otherwise occur with multiple sequential transmissions.
Solution Approach 2:
The DMA controller serves as a mediator that handles the burden of managing multiple sequential transmissions. It automatically updates configurations, monitors transmission states, and coordinates between the CPU and SPI controller for the entire sequence of transmissions. This intermediary approach allows high throughput continuous transmissions while keeping CPU resource utilization low.
Data Source
AI summary
A method of updating registers, including: providing a bitmap register; providing a target register; establishing a mapping between each bit in the bitmap register and a corresponding target content block in the target register; providing a register update instruction, the register update instruction including: one or more flag bits at specified locations, wherein each flag bit corresponds to a bit in the bitmap register, indicating whether the target content block corresponding to the bit needs to be updated; wherein for each target content block indicated by the bit that needs to be updated, the register update instruction further comprises a new content of the target content block or a source of the new content; writing the one or more flag bits in the register update instruction into the bitmap register; and executing the register update instruction to update the target content blocks.