SPI Interface Data Reordering for Parallel Transmission
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Solution Overview
Problem
The existing SPI interfaces are limited in data transfer speed when the sending SPI interface can perform multiple reads but the receiving SPI interface cannot perform multiple writes, resulting in slower data transmission compared to parallel data transfer over multiple lines.
Innovation Solution
The method involves generating a second character string with characters rearranged to facilitate parallel transmission across multiple SPI interfaces, using direct memory access to split and reassemble the data, allowing faster transfer by utilizing additional SPI interfaces for data transfer from a module with multiple read capabilities to one with limited write capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted via a single MISO data line in traditional SPI interfaces, then the system is simple and easy to implement, but the data transmission speed is limited
Solution Approach 1:
The invention segments the data transmission path by dividing the character string into multiple substrings and transmitting them through different SPI interfaces (MISO0, MISO1, etc.) simultaneously. This allows parallel data transfer, increasing overall transmission speed while maintaining compatibility with standard SPI protocols at each interface level.
Solution Approach 2:
The invention transitions from single-dimensional sequential transmission through one MISO line to multi-dimensional parallel transmission through multiple MISO lines. By utilizing additional SPI interfaces that are normally dedicated to MOSI function, the system adds a spatial dimension to data transmission, enabling simultaneous data flow across multiple channels.
2Speed
If the MOSI connector is used in addition to MISO connector for data output in dual-read SPI interfaces, then data transmission speed increases, but the SPI interface requires special dual read mode switching
Solution Approach 1:
The invention makes the MOSI connector multi-functional by allowing it to serve as an additional data output line (MISO1) when the SPI interface operates in dual-read mode. This enables the same physical connector to perform both traditional MOSI function and additional MISO function, increasing data transmission capacity without adding external connectors.
Solution Approach 2:
The SPI interface dynamically switches between single-read mode and dual-read mode depending on the transmission requirements. The system can adaptively activate additional MISO functionality by switching to dual-read mode, providing flexible data transmission capabilities that adjust to the specific needs of the application.
3Speed
If parallel data transmission over multiple data lines is implemented, then data transmission speed increases, but the receiving SPI interface must be capable of multiple writing which is not available in all interfaces
Solution Approach 1:
Instead of requiring the receiving interface to have multi-write capability (the traditional approach for parallel reception), the invention inverts the approach by using multiple receiving interfaces (SPI0, SPI1, etc.) that each have standard single-write capability. The data is distributed across multiple interfaces for reception, then reassembled at the destination, making the system compatible with standard SPI interfaces.
4Loss of time
If data is transmitted via a single data line, then the SPI interface configuration is simple, but the boot process takes longer to complete
Solution Approach 1:
The system prepares for high-speed data transmission by configuring multiple SPI interfaces and establishing parallel data paths before the actual data transfer begins. The DMA controller is pre-configured with the necessary parameters and memory addresses, allowing immediate high-speed transmission once initiated, thus reducing overall boot process time.
Data Source
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Figure 3
Figure 4~5
AI summary
In a method for transferring the characters of a first string, in which the characters are concatenated in a first order, from a first electronic module (101) with a first storage unit (103) and a multi-readable SPI interface (104) to a second electronic module (102) with a second storage unit (109), several SPI interfaces (106, 107) and a memory direct access control unit (108), the following steps are performed: generating a second string, in which the characters are concatenated in a second order, from the first string and storing the second string in the first storage unit (103), transferring the characters from the first storage unit (103) via the SPI interface (104) of the first electronic module (101) to the SPI interfaces (106, 107) of the second electronic module (102), whereby the characters are divided into several substrings,each of which is transferred to a different SPI interface (106, 107) of the second electronic module (102), and transferring the characters from the SPI interfaces (106, 107) of the second electronic module (102) to the second memory unit (109) using the memory direct access control unit (108) so that the characters are stored in the second memory unit (109), wherein the second sequence is designed such that when stored in the second memory unit (109) the characters are concatenated in the first sequence so that the first string is restored.