SPI Control Circuit Using Shared Error Flag and Response Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with SPI communication capabilities require multiple dedicated terminals and wires for error detection and communication, leading to increased size and cost due to the complexity of terminal and wire configurations.
Innovation Solution
A semiconductor device configuration that uses a common set of wires for SPI communication, where the error flag signal functions as both the error flag and response signal, reducing the number of necessary terminals and wires by integrating these signals into existing communication lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated terminals and wires are provided for error detection in SPI communication, then error detection capability is improved, but device complexity and number of terminals increase
Solution Approach 1:
The SDO terminal and wire are made multi-functional by enabling them to transmit both normal data signals during SPI communication and error flag signals during error conditions. This allows the same physical infrastructure to serve multiple purposes, eliminating the need for separate dedicated error detection terminals and wires.
Solution Approach 2:
The error detection function is merged with the existing SPI communication function by using the same SDO terminal and wire for both purposes. The error flag signal is combined with the data signal transmission, allowing error information to be conveyed through the existing communication channel without requiring additional physical resources.
2Adaptability or versatility
If multiple dedicated terminals are provided for SPI communication and error detection, then communication and error detection functions are improved, but device size increases
Solution Approach 1:
The SDO terminal is designed to perform multiple functions: transmitting data during normal SPI communication and transmitting error flag signals during error conditions. This multi-functionality reduces the number of required terminals, thereby reducing the device footprint and size.
Solution Approach 2:
The error detection function is merged into the existing SPI communication interface by utilizing the SDO terminal and wire for both data transmission and error flag transmission. This consolidation reduces the overall device size by eliminating the need for separate dedicated error detection terminals.
3Reliability
If dedicated wires are provided for error flag transmission, then error detection reliability is improved, but manufacturing cost increases
Solution Approach 1:
The SDO wire is made multi-functional to carry both data signals during normal operation and error flag signals during error conditions. This eliminates the need for separate dedicated error detection wires, reducing manufacturing complexity and cost while maintaining error detection reliability.
Solution Approach 2:
The error flag transmission function is merged with the data transmission function by using the same SDO wire for both purposes. This consolidation reduces the number of wires required, simplifying manufacturing processes and reducing material costs while preserving error detection capabilities.
Data Source
AI summary
A control circuit provided in a semiconductor device receives an input data signal during a selection period in which a selection signal has a predetermined level in synchronization with a clock signal and performs a corresponding operation corresponding to the input data signal during the selection period or after the selection period. The control circuit holds an error flag indicating whether a specific error has occurred, outputs, during a part of the selection period, a response signal corresponding to the input data signal from a data output terminal and outputs, during another part of the selection period, an error flag signal corresponding to the value of the error flag from the data output terminal.