SPI Flash Memory Latency Reduction via Modified DWA Read Command

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Solution Overview

Problem

Flash memory devices exhibit high power consumption and slow operation speed, leading to increased memory latency that can hinder microprocessor performance, particularly due to inefficient communication protocols and alignment requirements in read operations.

Innovation Solution

Implementing a modified Double-Word Aligned (DWA) read command mode in memory devices, which allows for aligned address read operations by optionally clearing the least significant bits of the address, reducing the need for dummy cycles and improving CPU throughput and power efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If standard SPI read commands are used with alignment requirements, then communication protocol compatibility is maintained, but read latency increases due to dummy cycles

Engineering Contradiction:

Improveread latencyVSAvoidcommunication protocol complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent changes the address alignment parameter from 4-byte alignment to 2-byte alignment, allowing the least significant bit of the address to vary. This parameter change eliminates the need for dummy cycles while maintaining protocol compatibility, directly reducing read latency without increasing device complexity

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

Instead of requiring the host to generate aligned addresses and add dummy cycles for misaligned accesses, the patent inverts the approach by having the memory device accept any address and internally handle the alignment through its address decoding logic, thereby eliminating dummy cycles and reducing latency

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If flash memory is used for non-volatile storage, then data retention is improved, but operation speed deteriorates compared to volatile memory

Engineering Contradiction:

Improvedata retentionVSAvoidoperation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent changes the address alignment parameter to enable direct access without dummy cycles, improving the effective operation speed of flash memory while maintaining its non-volatile data retention characteristics, thereby reducing the speed penalty associated with flash memory usage

Inventive Principle:

Principle #35Parameter changes

3Productivity

If microprocessor performance is optimized, then processing speed improves, but sensitivity to memory latency increases

Engineering Contradiction:

Improveprocessing speedVSAvoidmemory latency sensitivity

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent prepares the memory system by implementing 2-byte aligned addressing that eliminates dummy cycles in advance, so that when the microprocessor issues read commands, the data is returned without unnecessary delays, thereby maintaining high processing speed without the penalty of memory latency sensitivity

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11704258B2Latency reduction in SPI flash memory devices

Publication Date: 2023.07.18 DIALOG SEMICONDUCTOR US INC

AI summary

A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.