SPI Header Update via POCI Pin for Data Ready Signaling

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Solution Overview

Problem

Existing SPI compliant embedded systems face challenges in efficiently controlling the timing of header transmission between controller and peripheral devices, leading to software customization and hardware inefficiencies, and lack a hardware-based approach for signaling data availability.

Innovation Solution

A hardware-based approach using the SPI protocol's POCI pin to signal data availability, allowing for atomic header updates without software overhead, and utilizing a dedicated interrupt pin for signaling in low pin count devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If software-based header transmission control is used in SPI compliant embedded systems, then flexibility in timing control is improved, but processor load increases and hardware efficiency decreases

Engineering Contradiction:

Improvetiming control flexibilityVSAvoidprocessor load

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The peripheral device autonomously manages header transmission timing by detecting write transactions to header registers and automatically updating the header on the POCI line, eliminating the need for continuous software intervention and reducing processor load while maintaining timing flexibility

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent replaces software-based timing control with a hardware mechanism that uses write transaction detection circuitry and automatic header update logic to control transmission timing, improving hardware efficiency while preserving operational flexibility

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Loss of information

If software-based data availability signaling is implemented, then data readiness indication is achieved, but processing overhead increases

Engineering Contradiction:

Improvedata availability signalingVSAvoidprocessing overhead

Core Design Contradiction:

Loss of informationVSLoss of energy

Solution Approach 1:

The peripheral device automatically signals data availability by detecting when data is loaded into its output buffer and asserting the data ready signal, eliminating the need for software polling or interrupt handling and reducing processing overhead

Inventive Principle:

Principle #25Self-service

3Loss of information

If dedicated interrupt pin is used for data ready signaling in low pin count devices, then data availability indication is improved, but pin utilization complexity increases

Engineering Contradiction:

Improvedata ready signalingVSAvoidpin configuration

Core Design Contradiction:

Loss of informationVSDevice complexity

Solution Approach 1:

The dedicated interrupt pin serves multiple functions including data ready signaling, header availability indication, and general-purpose interrupt generation, allowing efficient use of limited pins while maintaining clear data availability signaling capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260017210A1Methods, systems, apparatus, and articles of manufacture to update headers and signal availability of data

Publication Date: 2026.01.15 TEXAS INSTRUMENTS INC

AI summary

An example device includes a peripheral out, controller in (POCI) pin. The device includes a buffer coupled to the POCI pin, wherein the device is configured to: detect a write transaction for a header that is addressed to a register, and cause the header to be written to the buffer in response to detecting the write transaction addressed to the register. Other examples are described.