Daisy-Chain SPI Writes Using Ignore Commands and Clocked Reset
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Solution Overview
Problem
Conventional SPI systems face inefficiencies in addressing a single slave or subset of slaves in a daisy chain configuration, requiring superfluous reads and writes to all slaves when writing to a selected slave, and lack effective methods to reset locked-up systems without power cycling or using a CS signal.
Innovation Solution
Implementing a master device with circuitry to send specific data series including slave update data and ignore commands, and controlling a clock signal to perform targeted writes and resets in SPI daisy chain configurations, using NOP commands and predefined clock signals to achieve selective slave operations and internal resets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional daisy chain SPI system updates all slaves to write to any slave, then all slaves are synchronized, but writing to a single slave requires superfluous reads and writes for all other slaves
Solution Approach 1:
The patent segments the data stream by introducing slave identification codes that allow the master device to address specific slaves individually. Instead of treating all slaves uniformly, the system divides the communication into slave-specific segments, enabling selective writes without requiring all slaves to be updated.
Solution Approach 2:
The patent applies local quality by allowing different slaves to have different operational states simultaneously. Targeted slaves receive write commands and update their memory, while non-targeted slaves maintain their current state or enter idle mode, rather than forcing uniform updates across all slaves.
2Reliability
If power cycle is used to reset locked-up SPI system, then system is reset, but power cycling is often impractical or impossible
Solution Approach 1:
The patent implements self-service reset capability where the SPI system can reset itself through software commands without external power cycling. The master device can initiate reset sequences that restore slaves to a known good state, allowing the system to recover from locked-up conditions autonomously.
Solution Approach 2:
The patent makes the reset function universal by implementing a standardized reset mechanism that works across different slave devices and can be initiated from the master device. This multi-functional approach allows the same communication interface to be used for both normal data transfer and system reset operations.
3Reliability
If chip select signal is used to reset slave devices, then reset is achieved, but CS is used for another purpose and is not available for system reset function
Solution Approach 1:
The patent makes the chip select signal multi-functional by using it for both its traditional purpose of selecting slaves for data transfer and as a trigger for reset operations. By encoding reset commands within the existing CS signal framework, the system achieves reset capability without requiring additional dedicated reset lines.
Solution Approach 2:
The patent introduces software intermediaries (command protocols) that mediate between the chip select signal and the reset function. Instead of directly using CS as a hardware reset line, the system uses software-based reset commands transmitted during the chip select period, allowing the same signal to serve multiple purposes.
Data Source
AI summary
A system includes a master device and multiple slave devices connected in a daisy chain arrangement, and configured to communicate according to a serial peripheral device interface (SPI) protocol. The master device includes circuitry to clock a series of bits into respective shift registers of the multiple slave devices, including (a) first data clocked into first shift registers of a first slave device and (b) an ignore command clocked into second shift registers of a second slave device, and use a clock signal to communicate an execute instruction to the plurality of slave devices. The execute instruction causes the first slave device to write the first data from the first shift registers to a first memory of the first slave device, whereas the execute instruction causes the second slave device to execute the ignore command to preclude a data write at a second memory of the second slave device.