SPI Master Client Communication with Programmable Response Delays

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Solution Overview

Problem

Processor-based emulation systems face challenges in communicating with clients due to non-deterministic response delays over communication interfaces like SPI, where there is no mechanism to confirm the status of write and read operations, and the clock rate is limited by round-trip delay times, making it difficult to ensure reliable and efficient data transfer.

Innovation Solution

The system configures hardware registers in communication interface clients with communication parameters that allow for programmable response times and periodic pinging by the master, enabling deterministic response delays and reliable data capture, thus removing the constraint of round-trip delay on clock rate and allowing for faster communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the SPI master and SPI client use opposite ends of the clock for data capture, then data transmission can occur, but the clock rate is limited by round-trip delay time

Engineering Contradiction:
Improveclock rateVSAvoidround-trip delay time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The system performs preliminary configuration of hardware registers with communication parameters including predetermined time intervals for pinging and programmable wait times for response generation. This preparation allows the client to respond at predetermined times without real-time decision-making delays, effectively decoupling the clock rate from round-trip delay constraints.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts communication timing by allowing the master to periodically ping the client at predetermined intervals and the client to generate responses based on programmable wait times. This dynamic timing mechanism enables adaptive synchronization that maintains reliable communication while supporting higher clock rates independent of fixed round-trip delays.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the SPI master implements write and read commands without confirmation mechanisms, then communication is simpler, but there is no way to confirm the status of operations or data validity

Engineering Contradiction:
Improveoperation status confirmationVSAvoidcommunication protocol complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system implements feedback mechanisms where the master periodically pings the client and the client generates response messages containing status information. The hardware registers are configured with communication parameters that enable the client to send acknowledgment messages confirming write operation completion and read data validity. This feedback loop provides reliable operation status confirmation while maintaining manageable protocol complexity through structured register-based communication.

Inventive Principle:
Principle #23Feedback

3Productivity

If the SPI client is constrained to meet shorter response time for specified clock rate, then faster communication is possible, but the client design becomes severely constrained

Engineering Contradiction:
Improvecommunication speedVSAvoidclient design flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The system changes the timing parameters from fixed round-trip delay constraints to configurable communication parameters stored in hardware registers. The master can set predetermined time intervals for pinging, and the client can use programmable wait times to determine response timing. This parameterization allows the client to respond at predetermined times based on configured values rather than hard constraints, enabling faster communication while maintaining design flexibility and adaptability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11301414B1Systems and methods for communicating with clients with non-deterministic response delay over a communication interface
Publication Date: 2022.04.12 CADENCE DESIGN SYST INC
  • US11301414B1 patent drawing
  • US11301414B1 patent drawing
  • US11301414B1 patent drawing

AI summary

A SPI master may configure a set of hardware registers associated with a SPI client with a set of communication parameters. The SPI master may send a message to the SPI client. The SPI master may periodically ping the SPI client until the SPI master receives an acknowledgement message from the SPI client in response to the message from the SPI master. The SPI master may periodically ping the SPI client based upon the set of communication parameters configured by the SPI master in the set of hardware registers. The SPI master may receive the acknowledgement message from the SPI client. The SPI master may determine a status of a read operation or a write operation associated with the message based upon the acknowledgement message.