SPI Master Polling Multiple Slave Devices
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Solution Overview
Problem
Conventional SPI communication systems are inefficient in polling multiple slave devices, leading to increased processing time on the SPI bus and limited availability for normal device operations, especially in automotive applications, and existing solutions are complex and costly.
Innovation Solution
A communications system that allows simultaneous polling of multiple slave SPI devices using a master circuit with polling signal terminals and independently activatable CS terminals, enabling rapid refresh of watchdog timers without modifying the SPI clock signal or software, and allowing different groups of devices to be polled at different intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate frames are used to refresh each slave device sequentially, then each slave device can be refreshed individually, but the SPI bus time and processing resources are significantly occupied reducing availability for normal operations
Solution Approach 1:
The patent merges the refresh operations of multiple slave devices into a single SPI frame by introducing a polling signal that simultaneously activates multiple slave devices. This allows simultaneous refreshing of multiple watchdog timers within one frame, thereby reducing SPI bus occupation time and increasing bus availability for normal operations while maintaining reliable watchdog functionality.
Solution Approach 2:
The patent implements periodic polling signals that can be activated at different intervals for different groups of slave devices. This periodic action allows flexible refresh scheduling where critical devices can be polled more frequently while less critical devices are polled less often, optimizing both reliability and SPI bus utilization.
2Adaptability or versatility
If the number of slave devices is increased, then more functionality is provided, but the time required for complete polling sequences increases and may cause watchdog timeouts
Solution Approach 1:
By merging multiple slave device refresh operations into a single SPI frame using simultaneous polling signals, the patent enables the system to support a larger number of slave devices without proportionally increasing polling time. Multiple devices are refreshed in parallel within the same frame, preventing watchdog timeouts even as device count increases.
Solution Approach 2:
The patent segments slave devices into different groups that can be polled at different intervals. This segmentation allows critical devices to receive frequent refreshes while less critical devices are polled less often, enabling the system to accommodate more devices overall without compromising watchdog reliability for critical components.
3Productivity
If modified SPI protocols are used to allow different slave devices to communicate within the same frame, then communication speed is improved, but complex custom hardware is required which is significantly more expensive than standard SPI circuits
Solution Approach 1:
The patent introduces a polling signal terminal that can simultaneously activate multiple slave devices using standard SPI circuitry. This multi-functional approach allows a single polling signal to serve multiple devices without requiring specialized custom hardware, maintaining compatibility with standard SPI integrated circuits while achieving improved communication efficiency.
Solution Approach 2:
The slave devices are designed to respond to a common polling signal that activates them simultaneously. Each slave device autonomously responds to the polling signal and its individual chip select signal, eliminating the need for complex centralized control hardware and reducing overall system complexity while maintaining fast polling capability.
Data Source
AI summary
Communications system including a master circuit having a master serial peripheral interface, SPI, device with an input MISO terminal. A plurality of slave circuits is provided for communication with the master circuit. Each slave includes a slave SPI device, an activation terminal, and an output switch for connecting an output MISO terminal to the input MISO terminal. The master circuit also includes a polling signal terminal for transmitting a polling signal to at least a first group of slave SPI devices for activating them. The master circuit 3 also has a plurality of output CS terminals, each being independently activatable to activate both the respective slave SPI device and the associated output switch.