Multi-Channel SPI Memory Controller for Direct Program Execution
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Solution Overview
Problem
Existing multi-channel SPI interface memories cannot directly execute programs, requiring program copying to SDRAM or SRAM, which occupies valuable memory resources and limits functionality.
Innovation Solution
A method and apparatus that enable program execution on multi-channel SPI interface memory by establishing a mechanism for CPU interaction with the memory, including state machine control logic, separate data and control paths, and registers for managing operations, allowing direct program execution and enhanced data processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a parallel memory interface is used, then data transmission rate is high, but the number of pins and interconnection cost increase
Solution Approach 1:
The patent segments the data transmission into multiple serial channels (4 channels) that can operate simultaneously. Each channel transmits data sequentially bit-by-bit, but the parallel operation of multiple channels achieves high aggregate throughput while using only 6 physical pins (CS, CLK, IO0-2), thus resolving the contradiction between transmission speed and pin count.
Solution Approach 2:
The patent transitions from a single wide parallel bus to multiple narrow serial channels, effectively adding the dimension of time multiplexing. By transmitting multiple bytes simultaneously through different channels at different time slots, the system achieves parallel throughput using a serial interface, resolving the pin count versus speed trade-off.
2Ease of operation
If program is copied to SDRAM or SRAM for execution, then program can be executed, but valuable memory resources are occupied
Solution Approach 1:
The patent makes the SPI flash memory multi-functional by integrating a program execution engine directly into the memory device. The memory can now serve both as data storage and as a programmable processor, eliminating the need for separate SDRAM/SRAM for program execution and thus preserving valuable memory resources for data storage.
Solution Approach 2:
The SPI flash memory becomes self-sufficient by incorporating an internal execution engine that can directly run programs stored in its own memory cells. This self-service capability eliminates the need to copy programs to external memory for execution, allowing the memory to handle both storage and processing functions independently.
3Adaptability or versatility
If program is copied to SDRAM or SRAM for execution, then program execution is enabled, but functionality of memory is limited to saving data
Solution Approach 1:
The patent transforms the SPI flash memory from a single-function data storage device into a multi-functional system that can both store data and execute programs. The integrated execution engine enables the memory to perform computational tasks directly, vastly expanding its functionality beyond mere data saving and eliminating the time-consuming program copying process.
Solution Approach 2:
The patent merges the program execution engine with the SPI flash memory structure, combining storage and processing functions into a single integrated device. This consolidation eliminates the need for separate memory and processor components, reducing system complexity and eliminating the overhead of program copying between memory and processor.
Data Source
AI summary
A multi-channel SPI interface memory controller disposed between a CPU and a multi-channel SPI interface memory is provided in the present invention. The multi-channel SPI interface memory controller comprises: a data path interface coupled to a bus of the CPU; a control path interface coupled to the bus of the CPU; a master controller coupled to the multi-channel SPI interface memory; a register bank disposed between the master controller and the control path interface, wherein the master controller is in signal coupling with the data path interface, and in signal coupling through the register bank with the control path interface. The inventive multi-channel SPI interface memory controller can support direct execution of a program on the SPI interface memory.