SPI Mode Switching for External Program Loading Compatibility
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Solution Overview
Problem
The limited internal memory in SPI microcontrollers restricts their functionality due to the need for external processors to provide programs quickly, limiting hardware specifications and performance thresholds.
Innovation Solution
A method and system that allows SPI microcontrollers to operate in both master and slave modes based on logic states of input/output terminals, enabling them to receive data from a master central process unit at a different operational clock speed, thus reducing hardware and performance thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SPI microcontroller operates as slave with external processor providing programs, then cost is reduced and I/O functions are expanded, but the external processor's hardware specification and performance threshold are severely limited
Solution Approach 1:
The SPI microcontroller dynamically switches between master and slave modes based on the operational requirements. When connected to an external processor, it operates in slave mode to extend I/O functions. When connected to a master controller, it switches to master mode to provide full functionality, thereby adapting to different system configurations and resolving the contradiction between versatility and performance threshold.
Solution Approach 2:
The system changes the operational mode parameter of the SPI microcontroller between master and slave configurations. This parameter change allows the same hardware to function differently depending on the connection type, enabling it to either extend I/O functions as a slave or operate independently as a master, thus eliminating the performance threshold limitation.
2Ease of manufacture
If SPI microcontroller uses external storage device for user programs, then chip cost is reduced and space is saved for expanded functions, but the external processor must provide programs quickly within strict time limits
Solution Approach 1:
The SPI microcontroller dynamically adjusts its operational mode based on the master clock frequency. When operating as slave with external processor, it uses the master's clock signal. When operating as master, it generates its own clock at appropriate speeds, allowing flexible timing adaptation that eliminates strict time limits for program provision while maintaining cost benefits of external storage.
Solution Approach 2:
The system changes the clock frequency parameter adaptively. As a slave, it synchronizes to the master's clock frequency. As a master, it can operate at various frequencies including 5 MHz minimum, allowing sufficient time for program provision while maintaining the cost advantage of using external storage devices.
3Adaptability or versatility
If SPI microcontroller operates at minimum 5 MHz clock frequency, then compatibility is maintained, but the external processor has only 0.2 µS to determine memory address and prepare information
Solution Approach 1:
The SPI microcontroller dynamically adjusts its clock frequency based on the operational mode and system requirements. While maintaining compatibility with minimum 5 MHz frequencies, it can operate at higher frequencies when needed, thereby increasing data transmission speed without sacrificing compatibility. This dynamic adjustment resolves the contradiction between maintaining compatibility and improving productivity.
Solution Approach 2:
The system changes the clock frequency parameter from a fixed minimum to a variable parameter. It can operate at 5 MHz for compatibility or at higher frequencies to improve data transmission speed. This parameter flexibility allows the system to adapt to different requirements, resolving the contradiction between compatibility and productivity.
Data Source
AI summary
A serial peripheral interface compatibility extension switching method and an embedded system using the same are provided in the present invention. The method includes: performing a reset to a SPI controller; providing a first logic voltage to at least one of the MOSI terminal, the MISO terminal and SPI clock terminal of a SPI port of the SPI controller; and transmitting or receiving data from the SPI port according to an external clock signal.