SPI NAND Memory Controller Mode Switching
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Solution Overview
Problem
NAND flash memory devices are not well-suited for serial peripheral interface (SPI) communication due to their page-based readout nature, which limits their functionality and requires unwieldy translations from SPI to standard NAND, thereby reducing their usefulness in applications where random access is necessary.
Innovation Solution
An SPI NAND memory device is configured with a controller that uses a serial peripheral interface protocol, enabling communication through four interface pins (CS, SCK, SI, and SO) and allowing access to volatile memory registers to control operational modes, including switching between SPI and NAND user modes, thereby enabling flexible operation and feature utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NAND flash memory devices use parallel communication with multiple input pins, then communication functionality is effective, but the device occupies more space on the IC chip
Solution Approach 1:
The patent merges multiple communication functions (data input, data output, address input, control signals) into a single bidirectional data bus. The controller internally routes different signal types through this shared bus, eliminating the need for separate dedicated pins for each function and reducing the overall pin count while maintaining full communication capability.
Solution Approach 2:
The bidirectional data bus serves multiple purposes: it carries data bidirectionally between master and slave, transmits address information, and conveys control signals. This multi-functional approach allows a single bus structure to replace what would traditionally require multiple separate signal lines, reducing device footprint.
2Area of stationary object
If the number of input pins is reduced for serial communication, then device space is reduced, but critical functionality is reduced
Solution Approach 1:
The controller dynamically switches the direction and function of the bidirectional data bus during operation. During write operations, the bus functions as input; during read operations, it functions as output. This dynamic reconfiguration allows a single bus to perform multiple functions that would traditionally require separate dedicated lines, maintaining full functionality with fewer pins.
Solution Approach 2:
The controller acts as an intermediary that translates between the simplified SPI protocol using the bidirectional bus and the internal NAND flash memory operations. It handles protocol conversion, timing synchronization, and signal routing, enabling full communication functionality through the constrained pin interface.
3Device complexity
If NAND flash memory uses page-based readout for SPI communication, then device complexity is reduced, but random access functionality is limited
Solution Approach 1:
Before performing a read operation, the controller receives and processes the full address information through the bidirectional bus, then pre-configures the internal memory addressing logic to enable direct random access to the requested location. This preliminary address setup allows the subsequent read operation to access any memory location directly, bypassing the need for sequential page-based access.
Solution Approach 2:
The controller changes the operational parameters of the NAND flash memory by interpreting SPI commands and translating them into appropriate internal memory operations. It modifies the address decoding behavior and readout mode to enable random access patterns, transforming the memory device from page-based sequential access to random access capability through parameter reconfiguration.
Data Source
AI summary
Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.