SPI NAND State Detection via Single-Cycle Flag

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Solution Overview

Problem

Conventional methods for determining the state of SPI NAND devices are power inefficient, particularly in IoT devices, due to the need for a large number of clock cycles to determine the busy state, which consumes excessive power and is not suitable for small, energy-efficient devices.

Innovation Solution

The method involves enabling the SPI NAND device using a first signal, such as the CS# signal, and receiving a flag indicating its state on the SO signal within a single clock cycle, reducing the number of clock cycles required to determine the device's status and thereby improving power efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If conventional methods are used to determine the state of SPI NAND devices, then the device state can be determined, but a large number of clock cycles are required which consumes excessive power

Engineering Contradiction:

Improvepower consumptionVSAvoidclock cycles required

Core Design Contradiction:

Use of energy by stationary objectVSLoss of time

Solution Approach 1:

The patent applies preliminary action by having the SPI NAND device prepare and output the busy flag on the SO line before the memory controller needs to check the device state. The device proactively updates the flag as soon as operations complete, so when the controller checks, the information is already available without requiring multiple polling cycles.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the SO (Slave Output) line to provide continuous state information from the SPI NAND device back to the memory controller. The busy flag on the SO line serves as real-time feedback about device operational status, eliminating the need for repeated query cycles and reducing power consumption.

Inventive Principle:

Principle #23Feedback

2Productivity

If a parallel interface is used for communication, then data transfer capability is improved, but the number of pins required increases which compromises device size

Engineering Contradiction:

Improvedata transfer capabilityVSAvoiddevice size

Core Design Contradiction:

ProductivityVSArea of moving object

Solution Approach 1:

The patent applies multi-functionality by making each pin in the SPI interface perform multiple functions. For example, the SO pin serves both as a data output line and as a status indicator (busy flag). The SCK pin provides both clocking and timing synchronization. This consolidation allows the interface to maintain robust communication capabilities while using fewer pins, reducing the device footprint for IoT applications.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10522201B2Methods and systems for serial memory device control

Publication Date: 2019.12.31 QUALCOMM INC

AI summary

Aspects of the present disclosure relate to systems and methods for determining a state of a serial memory device. Certain embodiments provide a method of determining a state of a serial memory device. The method includes enabling the serial memory device using a first signal. The method further includes receiving a flag indicating a state of the serial memory device based on the enabling of the serial memory device using the first signal.