SPI Peripheral Single Chip Select Control
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Solution Overview
Problem
SPI ROMs used in server applications can become corrupted over time, leading to reliability issues, and existing methods lack a robust mechanism for backing up their contents.
Innovation Solution
A computing system that controls multiple SPI peripherals using a single chip select, where the first SPI peripheral determines whether it is primary or backup based on a polarity signal, and accordingly services instructions or passes them to a second SPI peripheral, ensuring data integrity and backup functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single chip select is used to control multiple SPI peripherals, then device complexity is reduced, but it becomes difficult to distinguish which peripheral should service the instruction
Solution Approach 1:
Each SPI peripheral is assigned a unique local identifier (ID register value) that distinguishes it from others. When an instruction is received, each peripheral compares its local ID with the ID contained in the instruction to determine whether it should service the instruction, thus resolving the identification difficulty while maintaining single chip select simplicity
2Reliability
If SPI ROM contents are backed up in a second SPI peripheral, then reliability is improved, but device complexity increases due to additional peripherals
Solution Approach 1:
The backup functionality is merged with the primary SPI peripheral by using the same SPI bus and single chip select signal. The first SPI peripheral serves dual purposes: as the primary device during normal operation and as a pass-through device that forwards instructions to the second SPI peripheral (backup) when needed, thus achieving reliability improvement without proportionally increasing device complexity
3Reliability
If the first SPI peripheral acts as a pass-through device, then backup functionality is enabled, but processing speed may be reduced due to additional signal transmission steps
Solution Approach 1:
The first SPI peripheral dynamically changes its operational mode based on the instruction type and system state. It can operate as a primary servicing device for normal operations, as a pass-through device for backup operations, or as a forwarding device for response signals, thus optimizing speed for different operational scenarios while maintaining backup capability
Data Source
AI summary
Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.