SPI Communication Merging Read Write Operations

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Solution Overview

Problem

Conventional SPI communication requires two separate communication cycles for both read and write operations, leading to inefficiencies and increased communication time.

Innovation Solution

A method and system for SPI communication where a master device transmits a single data packet containing both a read register address and a write register address, along with write data, allowing the slave device to perform both operations in a single communication cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If separate communication cycles are used for read and write operations, then communication protocol simplicity is maintained, but communication time and efficiency deteriorate

Engineering Contradiction:
Improvecommunication efficiencyVSAvoidcommunication protocol complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines separate read and write operations into a single communication cycle. The master device transmits a composite data packet containing both read register address and write register address, allowing the slave device to perform both operations simultaneously, thereby reducing communication overhead and improving efficiency

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The data packet is segmented into distinct functional components: read register address portion, write register address portion, and write data portion. This segmentation allows the slave device to parse and execute different operations from a single transmitted packet, resolving the contradiction by maintaining protocol simplicity while enabling combined operations

Inventive Principle:
Principle #1Segmentation

2Loss of time

If two separate communication cycles are used for read and write operations, then data transmission accuracy is maintained, but communication time increases

Engineering Contradiction:
Improvecommunication timeVSAvoiddata transmission reliability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

By merging read and write operations into one communication cycle with a single data packet transmission, the patent eliminates the time gap between operations while maintaining data integrity through structured packet formatting that ensures reliable parsing and execution at the slave device

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If multiple data packets are sent for read and write operations, then operation completeness is ensured, but communication overhead increases

Engineering Contradiction:
Improvecommunication speedVSAvoiddata packet handling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The single data packet is segmented into clearly defined fields (read register address, write register address, write data) that the slave device can systematically parse. This segmentation approach ensures complete operation execution while reducing the number of packets transmitted, thereby improving communication speed without excessive complexity

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250110914A1Serial Peripheral Interface Communication System and Method
Publication Date: 2025.04.03 APTIV TECHNOLOGIES AG
  • US20250110914A1 patent drawing
  • US20250110914A1 patent drawing

AI summary

A method of serial peripheral interface (SPI) communication includes transmitting a data packet from a master device to a slave device. The data packet includes a read register address, a write register address, and write data. The read register address and the write register address correspond to a data register of a plurality of data registers of the slave device. The method includes receiving a portion of the data packet at the slave device. The portion of the data packet includes the read register address. The method includes reading the read register address in the data packet at the slave device. The method includes transmitting, from the slave device, data from the data register corresponding to the read register address of the slave device to the master device after the read register address has been read.