SPI Slave Device Clock Buffering for High-Speed Daisy Chain Communication
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Solution Overview
Problem
The existing SPI daisy chain data communication system faces limitations in achieving high-speed communication as the number of slave devices increases, due to increased load capacitance affecting the serial clock signal waveform, which restricts the number of devices that can be connected to a master device.
Innovation Solution
A data communication system where the master device transmits a clock signal to the first slave device, which internally transmits and buffers it for subsequent slave devices, allowing each slave device to receive and shift write data pieces and transmit read data pieces synchronously with the clock signal, reducing load on the clock signal wire and maintaining high-speed communication regardless of the number of slave devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of slave devices is increased in the SPI daisy chain system, then the system can support more devices, but the load capacitance on the clock signal wire increases causing waveform dullness and limiting high-speed communication
Solution Approach 1:
The patent divides the clock signal transmission into multiple independent wire segments. Instead of transmitting the clock signal through a single long wire connecting all slave devices, separate clock signal wires are provided for different groups or stages of slave devices. This segmentation reduces the load capacitance on each individual wire, preventing waveform dullness and enabling high-speed communication even when many slave devices are connected.
2Quantity of substance
If more slave devices are connected in the daisy chain, then the system capacity increases, but the communication speed decreases due to accumulated load capacitance
Solution Approach 1:
By segmenting the clock signal transmission into multiple wires, each wire carries the clock signal to a limited number of slave devices, reducing the total load capacitance per wire. This allows the system to maintain high communication speeds even when a large number of slave devices are connected, as each wire segment operates within optimal capacitance limits.
Solution Approach 2:
The patent transitions from a single-dimensional clock signal transmission (one wire for all devices) to a multi-dimensional approach by introducing multiple parallel clock signal wires. This dimensional change allows the system to scale to more devices without sacrificing communication speed, as the load is distributed across multiple transmission paths.
Data Source
AI summary
A master device transmits a clock signal to a first slave device together with a write data signal including write data pieces respectively corresponding to slave devices connected in cascade. Each slave device includes a buffer that receives the clock signal, outputs an amplified clock signal, and transmits the clock signal to a next stage slave device, and an information acquisition circuit that acquires information data pieces and reads them as read data pieces. The slave devices take in a series of write data pieces included in the write data signal while shifting them at the timing of the clock signal output from each of the master device and the buffer and transmit a read data signal including a series of read data pieces read from each information acquisition circuit to the master device via the first slave device while shifting them at the timing of the clock signal group.