SPI Slave Clock Generator for Signal Delay Compensation

Solution Overview

Problem

The conventional 4-wire SPI communication system is limited by signal time delays, which compress the setup time for latching in MISO data by the master device at high operating frequencies, thereby limiting the maximum operating frequency of the SPI.

Innovation Solution

The communication system employs an additional clock generator in the slave device to generate a delayed SCLK, which is sent to the master device via an additional SCLK pin, effectively eliminating the invalid time caused by signal time delays during read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the operating frequency of the SPI is increased, then the communication speed is improved, but the setup time for latching in MISO data is compressed due to signal time delays

Engineering Contradiction:

Improveoperating frequencyVSAvoidsetup time

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The slave device performs preliminary action by generating the delayed SCLK in advance before the read data becomes valid. The clock generator creates a SCLK signal with pre-calculated delay time that matches the propagation delay of the read data path, ensuring that when the data arrives at the master device, the clock is already positioned to properly latch the data without compressing the setup time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention changes the parameter of the SCLK signal by introducing a controlled time delay. The clock generator modifies the SCLK signal's timing parameter to compensate for the propagation delay in the data path. By adjusting the delay parameter of the clock signal to match the data path delay, the system maintains adequate setup time even at high operating frequencies.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If the operating frequency is increased, then the communication efficiency is improved, but the maximum operating frequency is limited by the invalid time caused by signal delays

Engineering Contradiction:

Improvecommunication efficiencyVSAvoidmaximum operating frequency

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The slave device performs preliminary action by generating the delayed SCLK in advance before the read data becomes valid. The clock generator creates a SCLK signal with pre-calculated delay time that matches the propagation delay of the read data path, ensuring that when the data arrives at the master device, the clock is already positioned to properly latch the data without compressing the setup time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention changes the parameter of the SCLK signal by introducing a controlled time delay. The clock generator modifies the SCLK signal's timing parameter to compensate for the propagation delay in the data path. By adjusting the delay parameter of the clock signal to match the data path delay, the system maintains adequate setup time even at high operating frequencies.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250139037A1Communication system with improved signal delay and slave device and operating method thereof

Publication Date: 2025.05.01 PIXART IMAGING INC

AI summary

There is provided a communication system including a master device and a slave device. The master device includes a first interface port and a second interface port. When the master device runs a read operation, the first interface port is used to output a serial clock to the slave device. The slave device includes a clock generator used to generate a delayed serial clock having the same phase as read data according to the serial clock. The second interface port is used to receive the delayed serial clock and the read data to eliminate a time delay in a data transaction.