SPI Slave Controller Clock Management for MCU Host Communication
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Solution Overview
Problem
In applications using SPI buses, data transfer control becomes increasingly difficult, especially with burst data, and there is a concern about power consumption in portable electronic devices powered by batteries.
Innovation Solution
An electronic device with a system clock and SPI clock that can be switched between active and inactive states, along with a serial bridge controller and SPI slave controller, to manage transactions efficiently, reducing power consumption and improving communication management between a microcontroller unit (MCU) and a host processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the SPI bus is used for data transfer between host processor and MCU, then communication capability is provided, but data transfer control becomes increasingly difficult with burst data
Solution Approach 1:
The patent introduces a serial bridge controller as an intermediary device between the host processor and the MCU. This controller includes a host serial interface that receives data from the host processor, a serial bus memory for buffering, and an SPI slave controller that manages SPI communication with the MCU. This intermediary structure simplifies the control complexity by handling burst data management and protocol conversion in the bridge controller, making the host processor's job easier while maintaining full communication capability.
2Reliability
If the SPI bus operates continuously to ensure data transfer, then communication reliability is maintained, but power consumption increases in portable devices
Solution Approach 1:
The patent implements periodic action by enabling the SPI bus and related components only when needed. The host serial interface includes an enable signal that activates the interface and associated clocks only during data transfer operations. The SPI slave controller generates enable signals that activate the SPI clock and system clock only when transactions are required. This periodic activation maintains communication reliability when needed while significantly reducing power consumption during idle periods in portable devices.
3Speed
If clocks remain active to ensure immediate data transfer response, then communication speed is maintained, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock signals conditional and dynamic rather than static. The system clock and SPI clock are enabled only when the host serial interface is active and data transfer is required. The SPI slave controller dynamically generates enable signals based on transaction needs, activating clocks only during actual data transfer operations. This dynamic clock management ensures immediate response when communication is needed while minimizing power consumption during idle periods.
4Productivity
If the host serial interface remains active for burst data handling, then data transfer efficiency is improved, but power consumption increases
Solution Approach 1:
The patent implements continuity of useful action by maintaining the host serial interface in an active state throughout the entire burst data transfer operation. Once activated, the interface remains active to handle multiple data transfers without requiring re-initialization, improving efficiency. The interface is kept active for the duration of the burst transaction, allowing continuous data flow to the serial bus memory and SPI controller, while power is consumed only during this useful action period rather than continuously.
Data Source
AI summary
An electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a serial controller coupled to the system clock, and a memory. A slave controller may generate a request active signal based upon a transaction request from a host and causing each of the system clock, SPI clock, and host interface into the active state, store request data in the memory, and switch the host interface to the inactive state based upon the request data being stored. The serial controller may process the request based upon the request active signal, and generate a request complete signal based upon the request being processed. The slave controller may switch the system clock to the inactive state based upon the request complete signal. The SPI clock may be switched to the inactive state based upon the request complete signal.