SPI Test Device Error Detection via Data Comparison

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Solution Overview

Problem

Conventional Serial Peripheral Interface (SPI) devices face challenges in accurately detecting and correcting errors during data communication between master and slave chips, leading to potential malfunctions due to the inability to determine whether errors occur in data transmission or reception.

Innovation Solution

A serial communication test device and method that includes an interface for data transmission and reception, a register for error-checking data, a data storage unit for storing received data, a comparison unit for comparing stored and received data, and an error check controller to determine data similarity, allowing for error detection and increased reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional error detection and correction methods are used in SPI communication, then error detection capability is provided, but the time required for error detection and correction becomes significantly long

Engineering Contradiction:
Improveerror detection capabilityVSAvoidtime for error detection and correction
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The invention applies preliminary action by pre-storing transmitted data in a data storage unit before the comparison operation. When error detection is needed, the stored data is immediately compared with received data without requiring re-transmission or external storage access, thus significantly reducing the time for error detection while maintaining reliable error detection capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention creates a copy of the transmitted data by storing it in the data storage unit. This copy can be directly compared with the received data to detect errors, eliminating the need for re-transmission and reducing error detection time while ensuring accurate error detection through direct comparison

Inventive Principle:
Principle #26Copying

2Speed

If conventional SPI communication is used without error checking, then communication speed is maintained, but the ability to determine error location between master and slave chips is lost

Engineering Contradiction:
Improvecommunication speedVSAvoiderror location determination
Core Design Contradiction:
SpeedVSDifficulty of detecting and measuring

Solution Approach 1:

The invention implements feedback by having the slave chip compare received data with stored transmitted data and provide error information back to the master chip. This feedback mechanism enables rapid error detection and location determination without requiring slow external intervention, thus maintaining communication speed while solving the error location determination problem

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The slave chip performs self-service by automatically comparing received data with its stored copy of transmitted data and autonomously determining errors. This self-service capability eliminates the need for external error checking equipment, maintaining communication speed while enabling accurate error location determination

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9378076B2Serial communication test device, system including the same and method thereof
Publication Date: 2016.06.28 HYUNDAI MOTOR CO LTD
  • US9378076B2 patent drawing
  • US9378076B2 patent drawing
  • US9378076B2 patent drawing

AI summary

A serial communication test device, a system including the same, and a method thereof are provided, which relate to a technology that allows a master chip and a slave ship for Serial Peripheral Interface (SPI) communication to double-check data to increase reliability. The serial communication test device includes an interface that is configured to transmit and receive data to and from an external chip. A controller is configured to store data to be error-checked in a register to output the stored data to the external chip through the interface and to store data received from the external chip through the interface in a data storage unit. The controller compares the data stored in the register with the data stored in the data storage unit and determines whether the data stored in the register is substantially similar to data to be error-checked.