SPI Interface Variable Byte Width Transmission
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Solution Overview
Problem
Conventional SPI interfaces are limited to 8-bit or 16-bit transmissions and lack flexibility in handling variable data widths, requiring bit-banging technology that results in significant software overhead and inefficient energy consumption, especially in applications where only necessary bits need to be transmitted.
Innovation Solution
An enhanced SPI module that allows for variable data width transmissions by using a special function register to control the operation, enabling modes where each byte can be truncated to a selected bit-count, and a finite state machine to generate variable clock pulses, supporting packet sizes from 9 to 16391 bits and byte sizes from 1 to 8 bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SPI interface is used with fixed 8-bit or 16-bit transmissions, then device compatibility is maintained, but flexibility in handling variable data widths is lost and energy consumption increases
Solution Approach 1:
The patent implements dynamic byte width configuration where each byte can be independently configured to transmit 1-8 bits based on data requirements. The SPI module includes control logic that dynamically adjusts the number of bits transmitted per byte according to configuration registers, enabling adaptive data width selection rather than fixed 8-bit or 16-bit transmissions. This dynamic adaptation reduces energy consumption by transmitting only the necessary number of bits for each data element.
Solution Approach 2:
The invention changes the parameter of byte width from fixed (8-bit or 16-bit) to variable (1-8 bits per byte). Configuration registers allow programming of the exact number of bits to transmit for each byte, and control logic modifies the transmission parameter dynamically based on the configured values. This parameter change enables precise control over data width to match actual information requirements, eliminating energy waste from transmitting excess bits.
2Adaptability or versatility
If bit-banging technology is used to achieve variable bit length transmission, then data width flexibility is obtained, but software overhead and processing complexity increase significantly
Solution Approach 1:
The patent introduces an intermediary hardware control logic unit between the processor and the SPI transmission mechanism. This control logic receives configuration from registers and automatically generates the appropriate number of clock pulses and controls the transmission of variable bit lengths without requiring processor intervention for each bit. The intermediary hardware layer handles the complexity of variable width transmission, freeing the processor from bit-banging software overhead while maintaining flexibility.
Solution Approach 2:
The invention replaces the software-based bit-banging mechanism with hardware-based control logic. Instead of using processor instructions to manually control each bit transmission timing and duration, the patent implements dedicated hardware circuitry with configuration registers that automatically control the SPI transmission parameters. This substitution of software control with hardware control eliminates the significant software overhead associated with bit-banging while preserving variable bit length capability.
3Ease of operation
If excess bits are transmitted to maintain fixed 8-bit byte alignment, then transmission simplicity is maintained, but energy consumption increases and battery life decreases
Solution Approach 1:
The patent extracts and transmits only the necessary bits required for each data element rather than transmitting complete 8-bit bytes. The configuration registers specify the exact number of valid bits in each byte, and the control logic extracts and transmits only those bits while suppressing transmission of remaining bits. This extraction of essential information eliminates energy consumption associated with transmitting excess alignment bits while maintaining transmission simplicity through automated hardware control.
4Ease of manufacture
If standard SPI peripheral module is used with fixed byte size, then hardware implementation is simple, but support for complex data transfer requirements like Keeloq and PIC programming is limited
Solution Approach 1:
The patent implements a universal SPI module that can adapt to multiple protocols and data transfer requirements through configuration registers. The same hardware implementation supports variable byte widths (1-8 bits), variable packet sizes, and different transmission modes by programming the configuration registers with appropriate values. This multi-functionality allows a single simplified hardware design to support complex data transfer requirements such as Keeloq encryption protocols and Microchip PIC programming without requiring protocol-specific hardware modifications.
Data Source
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AI summary
A synchronous serial peripheral device has a transmission unit coupled with a data output line and a clock unit coupled with a clock line. The serial peripheral device transmits a minimum of a single transmission, wherein in a first operating mode the transmission unit and the clock unit are configurable to perform a data transmission with a data length that can be defined to be between one (1) and eight (8) bit.