SPICE Netlist PSL Assertion Circuit Verification
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Solution Overview
Problem
Current circuit simulators, such as SPICE, lack the capability to effectively verify complex conditions involving time-varying or circuit-varying conditions, particularly in analog circuit simulations, as they cannot monitor multiple voltages on multiple nodes or verify complex output voltage ranges over predefined times, limiting their ability to ensure proper operation of intricate circuits.
Innovation Solution
The integration of Property Specification Language (PSL) or SystemVerilog Assertions (SVA) syntax within the SPICE netlist allows for the definition of verification rules that can check for convergence, voltage thresholds, and temporal changes, enabling the verification of circuit states and operations based on predefined conditions, thereby extending the simulator's ability to handle complex analog and mixed-signal circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional SPICE netlist format is used for circuit simulation, then the simulator can perform basic circuit analysis, but it cannot verify complex time-varying conditions or monitor multiple voltages on multiple nodes
Solution Approach 1:
The patent merges the SPICE netlist format with PSL/SVA assertion syntax to create a unified verification system. The netlist language is extended to include assertion statements that can monitor circuit conditions, triggering verification checks without requiring separate verification tools or complex external scripting languages.
Solution Approach 2:
The extended netlist language serves multiple functions: it describes circuit topology, performs simulation analysis, and executes verification checks all within a single unified format. This eliminates the need for separate verification languages and tools, making the system more versatile while maintaining a consistent syntax.
2Reliability
If assert statements are added to SPICE netlist, then verification of circuit conditions becomes possible, but the netlist language becomes more complex
Solution Approach 1:
The patent introduces PSL/SVA assertion syntax as an intermediary layer between the circuit description and the verification logic. This standardized assertion language acts as a mediator that simplifies the verification process by providing a clear, formal way to specify conditions without embedding complex verification logic directly into the netlist structure.
3Adaptability or versatility
If complex verification rules are implemented, then the ability to monitor multiple voltages and verify temporal conditions improves, but the difficulty of detecting and measuring increases
Solution Approach 1:
The verification system segments complex verification rules into discrete assertion statements, each monitoring specific conditions independently. This allows the system to break down complex temporal and voltage monitoring tasks into manageable units that can be evaluated separately, reducing the overall difficulty of detection and measurement.
Data Source
AI summary
Systems and methods for simulating and verifying a design are contemplated. Various embodiments determine a set of verification rules for a design, wherein the verification rules use a PSL or SVA syntax in a SPICE netlist to describ a property of the circuit design. The state of a circuit at a simulated first time, t1, can be determined. The state at the first time, t1, may be analyzed to determine if a triggering event has occurred. Based on the occurrence of the triggering event, the systems and methods can verify the state at the first time, t1, against the set of verification rules. Some embodiments of the systems and methods described herein can include a mixed-signal circuit including an analog portion and a digital portion, and the analog portion, the mixed-signal portion, or both, may be simulated and verified.