Spider Test Pad Structure for 3DIC Connectivity Verification
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Solution Overview
Problem
As complexity increases in 3DIC devices, verifying proper electrical connectivity through metallization layers and identifying known good dies becomes increasingly challenging during fabrication, necessitating the incorporation of test pads in various metallization layers.
Innovation Solution
The implementation of test pads, such as the 'spider pad' design, which includes a frame, grid features, and a panel region, within different metallization layers to facilitate in situ testing and verify electrical connectivity during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more components are integrated into a given area to improve integration density, then integration density is improved, but verification of electrical connectivity and identification of known good dies becomes increasingly challenging
Solution Approach 1:
The patent divides the verification function into separate test pads that are distributed across different metallization layers. Each test pad is a discrete structure that can be independently accessed and tested, segmenting the complex verification task into manageable units that can be probed individually despite the high integration density of the overall device
Solution Approach 2:
The test pads serve as intermediary structures between the external testing equipment and the internal circuitry. These pads provide accessible contact points on the device surface that mediate the connection between probe cards and the underlying metallization layers, enabling electrical connectivity verification without requiring direct access to internal interconnects
2Ease of operation
If test pads are incorporated in various metallization layers to facilitate in situ testing, then ease of testing is improved, but device complexity increases
Solution Approach 1:
The test pads are designed with a universal structure that can be implemented across multiple metallization layers using the same design paradigm. Each test pad consists of a pad region, grid features, and opening in a dielectric layer, creating a multi-functional element that serves both as an electrical contact point and as a testing access point, thereby facilitating in situ testing without requiring fundamentally different structures for each layer
Solution Approach 2:
The test pad structure employs a nested configuration where the grid features are positioned within the pad region, and the opening in the dielectric layer is positioned to provide access to the grid features. This nested arrangement integrates multiple functional elements (pad region for electrical contact, grid features for mechanical support and electrical connection, opening for probe access) into a compact hierarchical structure that minimizes the overall footprint and reduces device complexity
Data Source
AI summary
Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.