Spider Test Pad Structure for Low-Dishing Wafer Probing
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Solution Overview
Problem
As semiconductor devices become more complex and feature sizes shrink, verifying proper electrical connectivity and identifying known good dies during fabrication of 3DIC devices becomes increasingly challenging, leading to issues such as dishing and damage from probing that affect the accuracy of wafer acceptance testing.
Innovation Solution
The integration of test pads with a spider pad design, featuring a frame, grid features, and a panel region, which minimizes dishing and reduces damage during chemical mechanical planarization and probing, allowing for robust electrical contact and effective testing throughout the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test pad structures are used, then electrical connectivity verification is achieved, but dishing and damage occur during chemical mechanical planarization and probing
Solution Approach 1:
The test pad structure is segmented into multiple functional regions: a frame region providing structural support, a grid region with interconnected conductive lines forming a lattice pattern, and a panel region for electrical contact. This segmentation allows each region to perform its specific function optimally while distributing mechanical stresses, thereby reducing dishing and damage during CMP and probing operations.
Solution Approach 2:
Different regions of the test pad are assigned different local qualities and functions. The frame region provides structural reinforcement, the grid region offers electrical connectivity with controlled resistance, and the panel region optimizes for electrical contact. This local differentiation allows the structure to maintain integrity while performing electrical verification, resolving the contradiction between reliability and manufacturing precision.
2Productivity
If feature sizes are reduced to improve integration density, then more components are integrated into a given area, but verifying electrical connectivity and identifying known good dies becomes increasingly challenging
Solution Approach 1:
The test pad structure transitions from traditional two-dimensional planar contacts to a three-dimensional grid lattice configuration. This dimensional change increases the effective electrical contact area and provides multiple parallel conduction paths, making electrical connectivity verification more reliable even as device feature sizes shrink and integration density increases.
Solution Approach 2:
The spider pad structure is integrated into the interconnect layers during the fabrication process itself, rather than being added as a separate post-processing element. This preliminary action allows electrical connectivity verification to be performed on known good dies during manufacturing, enabling early detection of defects and simplifying the identification of functional devices amidst high integration density.
Data Source
AI summary
Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.